arm64: zynqmp: Create description for generic SC (vpk120-revB)

System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 39aa30a241626a20938b6428a00d661a3f6464c2..81d4de5a99738163c3830bfa0637e16c00ce4c32 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -316,6 +316,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
        zynqmp-mini-qspi-x1-stacked.dtb         \
        zynqmp-mini-qspi-x2-single.dtb          \
        zynqmp-mini-qspi-x2-stacked.dtb         \
+       zynqmp-sc-revB.dtb                      \
        zynqmp-sm-k26-revA.dtb                  \
        zynqmp-smk-k26-revA.dtb                 \
        zynqmp-sck-kv-g-dp.dtbo                 \

diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
new file mode 100644 (file)
index 0000000..e60de50
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Generic System Controller
+ *
+ * (C) Copyright 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+       model = "ZynqMP Generic System Controller";
+       compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp";
+
+       aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               mmc0 = &sdhci0;
+               mmc1 = &sdhci1;
+               nvmem0 = &eeprom;
+               rtc0 = &rtc;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &dcc;
+               spi0 = &qspi;
+               spi1 = &spi0;
+               spi2 = &spi1;
+               usb0 = &usb0;
+               usb1 = &usb1;
+       };
+
+       chosen {
+               bootargs = "earlycon";
+               stdout-path = "serial1:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               autorepeat;
+               fwuen {
+                       label = "sw16";
+                       gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               ds40-led {
+                       label = "heartbeat";
+                       gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+               ds44-led {
+                       label = "status";
+                       gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+               };
+       };
+
+       si5332_2: si5332_2 { /* u42 */
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <26000000>;
+       };
+};
+
+&gpio {
+       status = "okay";
+};
+
+&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&phy0>;
+
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+               reset-delay-us = <2>;
+
+               phy0: ethernet-phy@1 {
+                       #phy-cells = <1>;
+                       reg = <1>;
+                       ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+                       ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+                       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                       ti,dp83867-rxctrl-strap-quirk;
+               };
+       };
+};
+
+&i2c1 { /* i2c1 MIO 24-25 */
+       status = "okay";
+       u-boot,dm-pre-reloc;
+       clock-frequency = <400000>;
+       /* No reason to do pinctrl setup at u-boot stage */
+
+       /* Use for storing information about SC board */
+       eeprom: eeprom@54 { /* u34 - m24128 16kB */
+               compatible = "st,24c128", "atmel,24c128";
+               reg = <0x54>; /* & 0x5c */
+               u-boot,dm-pre-reloc;
+       };
+};
+
+/* USB 3.0 only */
+&psgtr {
+       status = "okay";
+       /* nc, nc, usb3 */
+       clocks = <&si5332_2>;
+       clock-names = "ref2";
+};
+
+&qspi { /* MIO 0-5 */
+       status = "okay";
+       flash@0 {
+               compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <40000000>; /* 40MHz */
+               partition@0 {
+                       label = "Image Selector";
+                       reg = <0x0 0x80000>; /* 512KB */
+                       read-only;
+                       lock;
+               };
+               partition@80000 {
+                       label = "Image Selector Golden";
+                       reg = <0x80000 0x80000>; /* 512KB */
+                       read-only;
+                       lock;
+               };
+               partition@100000 {
+                       label = "Persistent Register";
+                       reg = <0x100000 0x20000>; /* 128KB */
+               };
+               partition@120000 {
+                       label = "Persistent Register Backup";
+                       reg = <0x120000 0x20000>; /* 128KB */
+               };
+               partition@140000 {
+                       label = "Open_1";
+                       reg = <0x140000 0xC0000>; /* 768KB */
+               };
+               partition@200000 {
+                       label = "Image A (FSBL, PMU, ATF, U-Boot)";
+                       reg = <0x200000 0xD00000>; /* 13MB */
+               };
+               partition@f00000 {
+                       label = "ImgSel Image A Catch";
+                       reg = <0xF00000 0x80000>; /* 512KB */
+                       read-only;
+                       lock;
+               };
+               partition@f80000 {
+                       label = "Image B (FSBL, PMU, ATF, U-Boot)";
+                       reg = <0xF80000 0xD00000>; /* 13MB */
+               };
+               partition@1c80000 {
+                       label = "ImgSel Image B Catch";
+                       reg = <0x1C80000 0x80000>; /* 512KB */
+                       read-only;
+                       lock;
+               };
+               partition@1d00000 {
+                       label = "Open_2";
+                       reg = <0x1D00000 0x100000>; /* 1MB */
+               };
+               partition@1e00000 {
+                       label = "Recovery Image";
+                       reg = <0x1E00000 0x200000>; /* 2MB */
+                       read-only;
+                       lock;
+               };
+               partition@2000000 {
+                       label = "Recovery Image Backup";
+                       reg = <0x2000000 0x200000>; /* 2MB */
+                       read-only;
+                       lock;
+               };
+               partition@2200000 {
+                       label = "U-Boot storage variables";
+                       reg = <0x2200000 0x20000>; /* 128KB */
+               };
+               partition@2220000 {
+                       label = "U-Boot storage variables backup";
+                       reg = <0x2220000 0x20000>; /* 128KB */
+               };
+               partition@2240000 {
+                       label = "SHA256";
+                       reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
+                       read-only;
+                       lock;
+               };
+               partition@2250000 {
+                       label = "User";
+                       reg = <0x2250000 0x1db0000>; /* 29.5 MB */
+               };
+       };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
+       status = "okay";
+       non-removable;
+       disable-wp;
+       bus-width = <8>;
+       xlnx,mio-bank = <0>;
+};
+
+&uart1 { /* uart0 MIO36-37 */
+       status = "okay";
+       u-boot,dm-pre-reloc;
+};
+
+&usb0 {
+       status = "okay";
+       pinctrl-names = "default";
+       phy-names = "usb3-phy";
+       phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+};
+
+&dwc3_0 {
+       status = "okay";
+       dr_mode = "host";
+       snps,usb3_lpm_capable;
+       maximum-speed = "super-speed";
+};
+