6.6-stable patches

added patches:
	riscv-fix-enabling-cbo.zero-when-running-in-m-mode.patch
	riscv-save-restore-envcfg-csr-during-cpu-suspend.patch

diff --git a/queue-6.6/riscv-fix-enabling-cbo.zero-when-running-in-m-mode.patch b/queue-6.6/riscv-fix-enabling-cbo.zero-when-running-in-m-mode.patch
new file mode 100644 (file)
index 0000000..bc77f8f
--- /dev/null
+++ b/queue-6.6/riscv-fix-enabling-cbo.zero-when-running-in-m-mode.patch
@@ -0,0 +1,54 @@
+From 3fb3f7164edc467450e650dca51dbe4823315a56 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel.holland@sifive.com>
+Date: Tue, 27 Feb 2024 22:55:33 -0800
+Subject: riscv: Fix enabling cbo.zero when running in M-mode
+
+From: Samuel Holland <samuel.holland@sifive.com>
+
+commit 3fb3f7164edc467450e650dca51dbe4823315a56 upstream.
+
+When the kernel is running in M-mode, the CBZE bit must be set in the
+menvcfg CSR, not in senvcfg.
+
+Cc: <stable@vger.kernel.org>
+Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20240228065559.3434837-2-samuel.holland@sifive.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/include/asm/csr.h   |    2 ++
+ arch/riscv/kernel/cpufeature.c |    2 +-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/riscv/include/asm/csr.h
++++ b/arch/riscv/include/asm/csr.h
+@@ -398,6 +398,7 @@
+ # define CSR_STATUS   CSR_MSTATUS
+ # define CSR_IE               CSR_MIE
+ # define CSR_TVEC     CSR_MTVEC
++# define CSR_ENVCFG   CSR_MENVCFG
+ # define CSR_SCRATCH  CSR_MSCRATCH
+ # define CSR_EPC      CSR_MEPC
+ # define CSR_CAUSE    CSR_MCAUSE
+@@ -422,6 +423,7 @@
+ # define CSR_STATUS   CSR_SSTATUS
+ # define CSR_IE               CSR_SIE
+ # define CSR_TVEC     CSR_STVEC
++# define CSR_ENVCFG   CSR_SENVCFG
+ # define CSR_SCRATCH  CSR_SSCRATCH
+ # define CSR_EPC      CSR_SEPC
+ # define CSR_CAUSE    CSR_SCAUSE
+--- a/arch/riscv/kernel/cpufeature.c
++++ b/arch/riscv/kernel/cpufeature.c
+@@ -679,7 +679,7 @@ arch_initcall(check_unaligned_access_boo
+ void riscv_user_isa_enable(void)
+ {
+       if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
+-              csr_set(CSR_SENVCFG, ENVCFG_CBZE);
++              csr_set(CSR_ENVCFG, ENVCFG_CBZE);
+ }
+ 
+ #ifdef CONFIG_RISCV_ALTERNATIVE

diff --git a/queue-6.6/riscv-save-restore-envcfg-csr-during-cpu-suspend.patch b/queue-6.6/riscv-save-restore-envcfg-csr-during-cpu-suspend.patch
new file mode 100644 (file)
index 0000000..ff36216
--- /dev/null
+++ b/queue-6.6/riscv-save-restore-envcfg-csr-during-cpu-suspend.patch
@@ -0,0 +1,55 @@
+From 05ab803d1ad8ac505ade77c6bd3f86b1b4ea0dc4 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel.holland@sifive.com>
+Date: Tue, 27 Feb 2024 22:55:35 -0800
+Subject: riscv: Save/restore envcfg CSR during CPU suspend
+
+From: Samuel Holland <samuel.holland@sifive.com>
+
+commit 05ab803d1ad8ac505ade77c6bd3f86b1b4ea0dc4 upstream.
+
+The value of the [ms]envcfg CSR is lost when entering a nonretentive
+idle state, so the CSR must be rewritten when resuming the CPU.
+
+Cc: <stable@vger.kernel.org> # v6.7+
+Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
+Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Link: https://lore.kernel.org/r/20240228065559.3434837-4-samuel.holland@sifive.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/include/asm/suspend.h |    1 +
+ arch/riscv/kernel/suspend.c      |    4 ++++
+ 2 files changed, 5 insertions(+)
+
+--- a/arch/riscv/include/asm/suspend.h
++++ b/arch/riscv/include/asm/suspend.h
+@@ -14,6 +14,7 @@ struct suspend_context {
+       struct pt_regs regs;
+       /* Saved and restored by high-level functions */
+       unsigned long scratch;
++      unsigned long envcfg;
+       unsigned long tvec;
+       unsigned long ie;
+ #ifdef CONFIG_MMU
+--- a/arch/riscv/kernel/suspend.c
++++ b/arch/riscv/kernel/suspend.c
+@@ -11,6 +11,8 @@
+ void suspend_save_csrs(struct suspend_context *context)
+ {
+       context->scratch = csr_read(CSR_SCRATCH);
++      if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
++              context->envcfg = csr_read(CSR_ENVCFG);
+       context->tvec = csr_read(CSR_TVEC);
+       context->ie = csr_read(CSR_IE);
+ 
+@@ -32,6 +34,8 @@ void suspend_save_csrs(struct suspend_co
+ void suspend_restore_csrs(struct suspend_context *context)
+ {
+       csr_write(CSR_SCRATCH, context->scratch);
++      if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
++              csr_write(CSR_ENVCFG, context->envcfg);
+       csr_write(CSR_TVEC, context->tvec);
+       csr_write(CSR_IE, context->ie);
+ 

diff --git a/queue-6.6/series b/queue-6.6/series
index 1717b281fb11af22af242e76ea330a54d5aa9ee2..96ed86197ffa4ab91a53b73ee142d81144514895 100644 (file)
--- a/queue-6.6/series
+++ b/queue-6.6/series
@@ -129,3 +129,5 @@ mm-hugetlb-add-huge-page-size-param-to-huge_ptep_get_and_clear.patch
 arm64-hugetlb-fix-huge_ptep_get_and_clear-for-non-present-ptes.patch
 kbuild-hdrcheck-fix-cross-build-with-clang.patch
 alsa-hda-realtek-fix-incorrect-is_reachable-usage.patch
+riscv-fix-enabling-cbo.zero-when-running-in-m-mode.patch
+riscv-save-restore-envcfg-csr-during-cpu-suspend.patch