drm/i915/display: convert i915_pipestat_enable_mask() to struct intel_display

Going forward, struct intel_display is the main display device data
pointer. Convert i915_pipestat_enable_mask() to struct intel_display,
allowing further conversions elsewhere.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/975b382c703cfb62f24643e40eac247b8e8bbea8.1739378096.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b8fcf74bd3acd57dd884dc9d341f19bf4ec19c0c..880eaed83cd5a2bf87c5a3274109c86554e7a3b7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -226,29 +226,30 @@ void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)
        ibx_display_interrupt_update(i915, bits, 0);
 }
 
-u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
+u32 i915_pipestat_enable_mask(struct intel_display *display,
                              enum pipe pipe)
 {
-       u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe];
+       struct drm_i915_private *dev_priv = to_i915(display->drm);
+       u32 status_mask = display->irq.pipestat_irq_mask[pipe];
        u32 enable_mask = status_mask << 16;
 
        lockdep_assert_held(&dev_priv->irq_lock);
 
-       if (DISPLAY_VER(dev_priv) < 5)
+       if (DISPLAY_VER(display) < 5)
                goto out;
 
        /*
         * On pipe A we don't support the PSR interrupt yet,
         * on pipe B and C the same bit MBZ.
         */
-       if (drm_WARN_ON_ONCE(&dev_priv->drm,
+       if (drm_WARN_ON_ONCE(display->drm,
                             status_mask & PIPE_A_PSR_STATUS_VLV))
                return 0;
        /*
         * On pipe B and C we don't support the PSR interrupt yet, on pipe
         * A the same bit is for perf counters which we don't use either.
         */
-       if (drm_WARN_ON_ONCE(&dev_priv->drm,
+       if (drm_WARN_ON_ONCE(display->drm,
                             status_mask & PIPE_B_PSR_STATUS_VLV))
                return 0;
 
@@ -261,7 +262,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
                enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 
 out:
-       drm_WARN_ONCE(&dev_priv->drm,
+       drm_WARN_ONCE(display->drm,
                      enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
                      status_mask & ~PIPESTAT_INT_STATUS_MASK,
                      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
@@ -288,7 +289,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
                return;
 
        dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;
-       enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+       enable_mask = i915_pipestat_enable_mask(display, pipe);
 
        intel_de_write(display, reg, enable_mask | status_mask);
        intel_de_posting_read(display, reg);
@@ -312,7 +313,7 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
                return;
 
        dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;
-       enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+       enable_mask = i915_pipestat_enable_mask(display, pipe);
 
        intel_de_write(display, reg, enable_mask | status_mask);
        intel_de_posting_read(display, reg);
@@ -525,7 +526,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 
                reg = PIPESTAT(dev_priv, pipe);
                pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
-               enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+               enable_mask = i915_pipestat_enable_mask(display, pipe);
 
                /*
                 * Clear the PIPE*STAT regs before the IIR

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
index b077712b7be1e0c701122130ea4116c271b37720..75ab38a0908e48b53b97785e22af8e752683ef48 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.h
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
@@ -11,8 +11,9 @@
 #include "intel_display_limits.h"
 
 enum pipe;
-struct drm_i915_private;
 struct drm_crtc;
+struct drm_i915_private;
+struct intel_display;
 
 void valleyview_enable_display_irqs(struct drm_i915_private *i915);
 void valleyview_disable_display_irqs(struct drm_i915_private *i915);
@@ -64,7 +65,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *i915);
 void gen11_de_irq_postinstall(struct drm_i915_private *i915);
 void dg1_de_irq_postinstall(struct drm_i915_private *i915);
 
-u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe);
+u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
 void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
 void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
 void i915_enable_asle_pipestat(struct drm_i915_private *i915);

diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 14b00988a81f5cc995b03b42d7d6c2337cc30da9..7a8fbff39be064350351f230e12c6fe623bcc0cb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -103,7 +103,7 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
        if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
                return;
 
-       enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
+       enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);
        intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
        intel_de_posting_read(display, reg);
 
@@ -121,7 +121,7 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
        lockdep_assert_held(&dev_priv->irq_lock);
 
        if (enable) {
-               u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+               u32 enable_mask = i915_pipestat_enable_mask(display, pipe);
 
                intel_de_write(display, reg,
                               enable_mask | PIPE_FIFO_UNDERRUN_STATUS);