--- /dev/null
+From 04850c4d8613127a9b488321c0ad83bff7519311 Mon Sep 17 00:00:00 2001
+From: Han Xu <b45815@freescale.com>
+Date: Fri, 23 Oct 2015 13:18:28 -0500
+Subject: mtd: fsl-quadspi: fix macro collision problems with READ/WRITE
+
+From: Han Xu <b45815@freescale.com>
+
+commit 04850c4d8613127a9b488321c0ad83bff7519311 upstream.
+
+Change the READ/WRITE to FSL_READ/FSL_WRITE to resolve any possible
+namespace collisions with READ/WRITE macros (e.g., from <linux/fs.h>).
+
+Problems have been seen, for example, on mips:
+
+>> drivers/mtd/spi-nor/fsl-quadspi.c:186:5: error: 'LUT_0' undeclared (first use in this function)
+ ((LUT_##ins) << INSTR0_SHIFT))
+ ^
+>> drivers/mtd/spi-nor/fsl-quadspi.c:188:30: note: in expansion of macro 'LUT0'
+
+On SPARC:
+
+drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
+drivers/mtd/spi-nor/fsl-quadspi.c:369:1: error: 'LUT_0' undeclared (first use in this function)
+drivers/mtd/spi-nor/fsl-quadspi.c:418:1: error: pasting "LUT_" and "(" does not give a valid preprocessing token
+drivers/mtd/spi-nor/fsl-quadspi.c:418:2: error: implicit declaration of function 'LUT_'
+
+And surely on others.
+
+Fixes: d26a22d06708 ("mtd: fsl-quadspi: allow building for other ARCHes with COMPILE_TEST")
+Reported-by: Guenter Roeck <linux@roeck-us.net>
+Reported-by: kbuild test robot <fengguang.wu@intel.com>
+Signed-off-by: Han Xu <b45815@freescale.com>
+[Brian: rewrote commit description]
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -138,15 +138,15 @@
+ #define LUT_MODE 4
+ #define LUT_MODE2 5
+ #define LUT_MODE4 6
+-#define LUT_READ 7
+-#define LUT_WRITE 8
++#define LUT_FSL_READ 7
++#define LUT_FSL_WRITE 8
+ #define LUT_JMP_ON_CS 9
+ #define LUT_ADDR_DDR 10
+ #define LUT_MODE_DDR 11
+ #define LUT_MODE2_DDR 12
+ #define LUT_MODE4_DDR 13
+-#define LUT_READ_DDR 14
+-#define LUT_WRITE_DDR 15
++#define LUT_FSL_READ_DDR 14
++#define LUT_FSL_WRITE_DDR 15
+ #define LUT_DATA_LEARN 16
+
+ /*
+@@ -306,7 +306,7 @@ static void fsl_qspi_init_lut(struct fsl
+
+ writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
++ writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
+
+ /* Write enable */
+@@ -327,11 +327,11 @@ static void fsl_qspi_init_lut(struct fsl
+
+ writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ base + QUADSPI_LUT(lut_base));
+- writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
++ writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+
+ /* Read Status */
+ lut_base = SEQID_RDSR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
++ writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Erase a sector */
+@@ -356,17 +356,17 @@ static void fsl_qspi_init_lut(struct fsl
+
+ /* READ ID */
+ lut_base = SEQID_RDID * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
++ writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Write Register */
+ lut_base = SEQID_WRSR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
++ writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Read Configuration Register */
+ lut_base = SEQID_RDCR * 4;
+- writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
++ writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
+ base + QUADSPI_LUT(lut_base));
+
+ /* Write disable */