--- /dev/null
+From ab7ee876c54c0c82d7fd8be267a5c44661e21d31 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Thu, 26 Apr 2018 17:28:00 +0200
+Subject: Revert "pinctrl: intel: Initialize GPIO properly when used through irqchip"
+
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+This reverts commit f5a26acf0162477af6ee4c11b4fb9cffe5d3e257
+
+Mike writes:
+ It seems that commit f5a26acf0162 ("pinctrl: intel: Initialize GPIO
+ properly when used through irqchip") can cause problems on some Skylake
+ systems with Sunrisepoint PCH-H. Namely on certain systems it may turn
+ the backlight PWM pin from native mode to GPIO which makes the screen
+ blank during boot.
+
+ There is more information here:
+
+ https://bugzilla.redhat.com/show_bug.cgi?id=1543769
+
+ The actual reason is that GPIO numbering used in BIOS is using "Windows"
+ numbers meaning that they don't match the hardware 1:1 and because of
+ this a wrong pin (backlight PWM) is picked and switched to GPIO mode.
+
+ There is a proper fix for this but since it has quite many dependencies
+ on commits that cannot be considered stable material, I suggest we
+ revert commit f5a26acf0162 from stable trees 4.9, 4.14 and 4.15 to
+ prevent the backlight issue.
+
+Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Fixes: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip")
+Cc: Daniel Drake <drake@endlessm.com>
+Cc: Chris Chiu <chiu@endlessm.com>
+Cc: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/intel/pinctrl-intel.c | 23 ++++++++---------------
+ 1 file changed, 8 insertions(+), 15 deletions(-)
+
+--- a/drivers/pinctrl/intel/pinctrl-intel.c
++++ b/drivers/pinctrl/intel/pinctrl-intel.c
+@@ -368,18 +368,6 @@ static void __intel_gpio_set_direction(v
+ writel(value, padcfg0);
+ }
+
+-static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
+-{
+- u32 value;
+-
+- /* Put the pad into GPIO mode */
+- value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
+- /* Disable SCI/SMI/NMI generation */
+- value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
+- value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
+- writel(value, padcfg0);
+-}
+-
+ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned pin)
+@@ -387,6 +375,7 @@ static int intel_gpio_request_enable(str
+ struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ void __iomem *padcfg0;
+ unsigned long flags;
++ u32 value;
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+
+@@ -396,7 +385,13 @@ static int intel_gpio_request_enable(str
+ }
+
+ padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
+- intel_gpio_set_gpio_mode(padcfg0);
++ /* Put the pad into GPIO mode */
++ value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
++ /* Disable SCI/SMI/NMI generation */
++ value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
++ value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
++ writel(value, padcfg0);
++
+ /* Disable TX buffer and enable RX (this will be input) */
+ __intel_gpio_set_direction(padcfg0, true);
+
+@@ -775,8 +770,6 @@ static int intel_gpio_irq_type(struct ir
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+
+- intel_gpio_set_gpio_mode(reg);
+-
+ value = readl(reg);
+
+ value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);