mips: dts: ralink: rt3050: update system controller node and its consumers

Current RT3050 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
index 23062333a76d7ffb41c0b0e970d648fa4c1396e4..a7d9bb9bc1afb706d1ee076977f1128782d10fb6 100644 (file)
--- a/arch/mips/boot/dts/ralink/rt3050.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
        #address-cells = <1>;
        #size-cells = <1>;
@@ -25,9 +27,11 @@
                #address-cells = <1>;
                #size-cells = <1>;
 
-               sysc@0 {
-                       compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
+               sysc: syscon@0 {
+                       compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon";
                        reg = <0x0 0x100>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
 
                intc: intc@200 {
@@ -50,6 +54,8 @@
                        compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
 
+                       clocks = <&sysc RT305X_CLK_UARTLITE>;
+
                        interrupt-parent = <&intc>;
                        interrupts = <12>;