arm64: zynqmp: Added data cells to access efuse

This patch adds data cells under nvmem node to
read efuse memory

Signed-off-by: Durga Challa <vnsl.durga.challa@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 0bcd6e282ad0f49dab264cd509b1711d6dee1607..8f64f3b39b7893ebd8d6dea7e38f0883ca1f53ca 100644 (file)
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -327,6 +327,55 @@
                soc_revision: soc_revision@0 {
                        reg = <0x0 0x4>;
                };
+               /* efuse access */
+               efuse_dna: efuse_dna@c {
+                       reg = <0xc 0xc>;
+               };
+               efuse_usr0: efuse_usr0@20 {
+                       reg = <0x20 0x4>;
+               };
+               efuse_usr1: efuse_usr1@24 {
+                       reg = <0x24 0x4>;
+               };
+               efuse_usr2: efuse_usr2@28 {
+                       reg = <0x28 0x4>;
+               };
+               efuse_usr3: efuse_usr3@2c {
+                       reg = <0x2c 0x4>;
+               };
+               efuse_usr4: efuse_usr4@30 {
+                       reg = <0x30 0x4>;
+               };
+               efuse_usr5: efuse_usr5@34 {
+                       reg = <0x34 0x4>;
+               };
+               efuse_usr6: efuse_usr6@38 {
+                       reg = <0x38 0x4>;
+               };
+               efuse_usr7: efuse_usr7@3c {
+                       reg = <0x3c 0x4>;
+               };
+               efuse_miscusr: efuse_miscusr@40 {
+                       reg = <0x40 0x4>;
+               };
+               efuse_chash: efuse_chash@50 {
+                       reg = <0x50 0x4>;
+               };
+               efuse_pufmisc: efuse_pufmisc@54 {
+                       reg = <0x54 0x4>;
+               };
+               efuse_sec: efuse_sec@58 {
+                       reg = <0x58 0x4>;
+               };
+               efuse_spkid: efuse_spkid@5c {
+                       reg = <0x5c 0x4>;
+               };
+               efuse_ppk0hash: efuse_ppk0hash@a0 {
+                       reg = <0xa0 0x30>;
+               };
+               efuse_ppk1hash: efuse_ppk1hash@d0 {
+                       reg = <0xd0 0x30>;
+               };
        };
 
        pcap: pcap {