KVM: arm64: Sanitise TCR2_EL2

TCR2_EL2 is a bag of control bits, all of which are only valid if
certain features are present, and RES0 otherwise.

Describe these constraints and register them with the masking
infrastructure.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Link: https://lore.kernel.org/r/20241023145345.1613824-13-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 26103d6514bd2af3096c1f50b670789455121e04..1c8a6aa907df1c812430c1a686253e30ddfeab22 100644 (file)
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -1204,6 +1204,28 @@ int kvm_init_nv_sysregs(struct kvm *kvm)
                res0 |= ~(res0 | res1);
        set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1);
 
+       /* TCR2_EL2 */
+       res0 = TCR2_EL2_RES0;
+       res1 = TCR2_EL2_RES1;
+       if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP))
+               res0 |= (TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1 | TCR2_EL2_D128);
+       if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, MEC, IMP))
+               res0 |= TCR2_EL2_AMEC1 | TCR2_EL2_AMEC0;
+       if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, HAFDBS, HAFT))
+               res0 |= TCR2_EL2_HAFT;
+       if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP))
+               res0 |= TCR2_EL2_PTTWI | TCR2_EL2_PnCH;
+       if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP))
+               res0 |= TCR2_EL2_AIE;
+       if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
+               res0 |= TCR2_EL2_POE | TCR2_EL2_E0POE;
+       if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP))
+               res0 |= TCR2_EL2_PIE;
+       if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP))
+               res0 |= (TCR2_EL2_E0POE | TCR2_EL2_D128 |
+                        TCR2_EL2_AMEC1 | TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1);
+       set_sysreg_masks(kvm, TCR2_EL2, res0, res1);
+
        /* SCTLR_EL1 */
        res0 = SCTLR_EL1_RES0;
        res1 = SCTLR_EL1_RES1;