dt-bindings: edac: Convert aspeed,ast2400-sdram-edac to DT schema

Convert the ASpeed SDRAM EDAC binding to DT schema. It's a
straight-forward conversion.

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Stefan Schaeckeler <sschaeck@cisco.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
new file mode 100644 (file)
index 0000000..0973582
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed BMC SoC SDRAM EDAC controller
+
+maintainers:
+  - Stefan Schaeckeler <sschaeck@cisco.com>
+
+description: >
+  The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
+  correction check).
+
+  The memory controller supports SECDED (single bit error correction, double bit
+  error detection) and single bit error auto scrubbing by reserving 8 bits for
+  every 64 bit word (effectively reducing available memory to 8/9).
+
+  Note, the bootloader must configure ECC mode in the memory controller.
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2400-sdram-edac
+      - aspeed,ast2500-sdram-edac
+      - aspeed,ast2600-sdram-edac
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    sdram@1e6e0000 {
+        compatible = "aspeed,ast2500-sdram-edac";
+        reg = <0x1e6e0000 0x174>;
+        interrupts = <0>;
+    };

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
deleted file mode 100644 (file)
index 8ca9e0a..0000000
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Aspeed BMC SoC EDAC node
-
-The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
-correction check).
-
-The memory controller supports SECDED (single bit error correction, double bit
-error detection) and single bit error auto scrubbing by reserving 8 bits for
-every 64 bit word (effectively reducing available memory to 8/9).
-
-Note, the bootloader must configure ECC mode in the memory controller.
-
-
-Required properties:
-- compatible: should be one of
-       - "aspeed,ast2400-sdram-edac"
-       - "aspeed,ast2500-sdram-edac"
-       - "aspeed,ast2600-sdram-edac"
-- reg:        sdram controller register set should be <0x1e6e0000 0x174>
-- interrupts: should be AVIC interrupt #0
-
-
-Example:
-
-       edac: sdram@1e6e0000 {
-               compatible = "aspeed,ast2500-sdram-edac";
-               reg = <0x1e6e0000 0x174>;
-               interrupts = <0>;
-       };

diff --git a/MAINTAINERS b/MAINTAINERS
index 4ee1f658c3c2f1d963b2970c95450cf5da969661..85eca954284d9736c59f9a1f79f9282ee46b3c09 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8695,7 +8695,7 @@ F:        drivers/edac/armada_xp_*
 EDAC-AST2500
 M:     Stefan Schaeckeler <sschaeck@cisco.com>
 S:     Supported
-F:     Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+F:     Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
 F:     drivers/edac/aspeed_edac.c
 
 EDAC-BLUEFIELD