+++ /dev/null
-From 0f5c8218c96029159b2bc09a358e2ffa0a305407 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 26 Feb 2024 13:07:22 -0400
-Subject: iommu/arm-smmu-v3: Check that the RID domain is S1 in SVA
-
-From: Jason Gunthorpe <jgg@nvidia.com>
-
-[ Upstream commit ae91f6552c301e5e8569667e9d5440d5f75a90c4 ]
-
-The SVA code only works if the RID domain is a S1 domain and has already
-installed the cdtable.
-
-Originally the check for this was in arm_smmu_sva_bind() but when the op
-was removed the test didn't get copied over to the new
-arm_smmu_sva_set_dev_pasid().
-
-Without the test wrong usage usually will hit a WARN_ON() in
-arm_smmu_write_ctx_desc() due to a missing ctx table.
-
-However, the next patches wil change things so that an IDENTITY domain is
-not a struct arm_smmu_domain and this will get into memory corruption if
-the struct is wrongly casted.
-
-Fail in arm_smmu_sva_set_dev_pasid() if the STE does not have a S1, which
-is a proxy for the STE having a pointer to the CD table. Write it in a way
-that will be compatible with the next patches.
-
-Fixes: 386fa64fd52b ("arm-smmu-v3/sva: Add SVA domain support")
-Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
-Closes: https://lore.kernel.org/linux-iommu/2a828e481416405fb3a4cceb9e075a59@huawei.com/
-Tested-by: Nicolin Chen <nicolinc@nvidia.com>
-Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
-Link: https://lore.kernel.org/r/11-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
-Signed-off-by: Will Deacon <will@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-index 8a16cd3ef487c..cc33e8297b8d0 100644
---- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-@@ -352,7 +352,13 @@ __arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm)
- struct arm_smmu_bond *bond;
- struct arm_smmu_master *master = dev_iommu_priv_get(dev);
- struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
-- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
-+ struct arm_smmu_domain *smmu_domain;
-+
-+ if (!(domain->type & __IOMMU_DOMAIN_PAGING))
-+ return -ENODEV;
-+ smmu_domain = to_smmu_domain(domain);
-+ if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1)
-+ return -ENODEV;
-
- if (!master || !master->sva_enabled)
- return ERR_PTR(-ENODEV);
---
-2.43.0
-
arm64-dts-rockchip-add-missing-interrupt-names-for-r.patch
arm64-dts-rockchip-fix-reset-names-for-rk356x-i2s2-c.patch
arm64-dts-rockchip-drop-rockchip-trcm-sync-tx-only-f.patch
-iommu-arm-smmu-v3-check-that-the-rid-domain-is-s1-in.patch
objtool-fix-unwind_hint_-save-restore-across-basic-b.patch
x86-relocs-ignore-relocations-in-.notes-section.patch
sunrpc-fix-a-memleak-in-gss_import_v2_context.patch
+++ /dev/null
-From 22d9d44f8fc0454d5932d8357f0c0aec3e44f292 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 26 Feb 2024 13:07:22 -0400
-Subject: iommu/arm-smmu-v3: Check that the RID domain is S1 in SVA
-
-From: Jason Gunthorpe <jgg@nvidia.com>
-
-[ Upstream commit ae91f6552c301e5e8569667e9d5440d5f75a90c4 ]
-
-The SVA code only works if the RID domain is a S1 domain and has already
-installed the cdtable.
-
-Originally the check for this was in arm_smmu_sva_bind() but when the op
-was removed the test didn't get copied over to the new
-arm_smmu_sva_set_dev_pasid().
-
-Without the test wrong usage usually will hit a WARN_ON() in
-arm_smmu_write_ctx_desc() due to a missing ctx table.
-
-However, the next patches wil change things so that an IDENTITY domain is
-not a struct arm_smmu_domain and this will get into memory corruption if
-the struct is wrongly casted.
-
-Fail in arm_smmu_sva_set_dev_pasid() if the STE does not have a S1, which
-is a proxy for the STE having a pointer to the CD table. Write it in a way
-that will be compatible with the next patches.
-
-Fixes: 386fa64fd52b ("arm-smmu-v3/sva: Add SVA domain support")
-Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
-Closes: https://lore.kernel.org/linux-iommu/2a828e481416405fb3a4cceb9e075a59@huawei.com/
-Tested-by: Nicolin Chen <nicolinc@nvidia.com>
-Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
-Link: https://lore.kernel.org/r/11-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
-Signed-off-by: Will Deacon <will@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-index 4a27fbdb2d844..2610e82c0ecd0 100644
---- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-@@ -364,7 +364,13 @@ static int __arm_smmu_sva_bind(struct device *dev, ioasid_t pasid,
- struct arm_smmu_bond *bond;
- struct arm_smmu_master *master = dev_iommu_priv_get(dev);
- struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
-- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
-+ struct arm_smmu_domain *smmu_domain;
-+
-+ if (!(domain->type & __IOMMU_DOMAIN_PAGING))
-+ return -ENODEV;
-+ smmu_domain = to_smmu_domain(domain);
-+ if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1)
-+ return -ENODEV;
-
- if (!master || !master->sva_enabled)
- return -ENODEV;
---
-2.43.0
-
arm64-dts-rockchip-add-missing-interrupt-names-for-r.patch
arm64-dts-rockchip-fix-reset-names-for-rk356x-i2s2-c.patch
arm64-dts-rockchip-drop-rockchip-trcm-sync-tx-only-f.patch
-iommu-arm-smmu-v3-check-that-the-rid-domain-is-s1-in.patch
objtool-fix-unwind_hint_-save-restore-across-basic-b.patch
x86-relocs-ignore-relocations-in-.notes-section.patch
sunrpc-fix-a-memleak-in-gss_import_v2_context.patch
+++ /dev/null
-From 47ae226f2334f7f8614671beeb7e90a554508077 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 26 Feb 2024 13:07:22 -0400
-Subject: iommu/arm-smmu-v3: Check that the RID domain is S1 in SVA
-
-From: Jason Gunthorpe <jgg@nvidia.com>
-
-[ Upstream commit ae91f6552c301e5e8569667e9d5440d5f75a90c4 ]
-
-The SVA code only works if the RID domain is a S1 domain and has already
-installed the cdtable.
-
-Originally the check for this was in arm_smmu_sva_bind() but when the op
-was removed the test didn't get copied over to the new
-arm_smmu_sva_set_dev_pasid().
-
-Without the test wrong usage usually will hit a WARN_ON() in
-arm_smmu_write_ctx_desc() due to a missing ctx table.
-
-However, the next patches wil change things so that an IDENTITY domain is
-not a struct arm_smmu_domain and this will get into memory corruption if
-the struct is wrongly casted.
-
-Fail in arm_smmu_sva_set_dev_pasid() if the STE does not have a S1, which
-is a proxy for the STE having a pointer to the CD table. Write it in a way
-that will be compatible with the next patches.
-
-Fixes: 386fa64fd52b ("arm-smmu-v3/sva: Add SVA domain support")
-Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
-Closes: https://lore.kernel.org/linux-iommu/2a828e481416405fb3a4cceb9e075a59@huawei.com/
-Tested-by: Nicolin Chen <nicolinc@nvidia.com>
-Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
-Link: https://lore.kernel.org/r/11-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
-Signed-off-by: Will Deacon <will@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-index 4a27fbdb2d844..2610e82c0ecd0 100644
---- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
-@@ -364,7 +364,13 @@ static int __arm_smmu_sva_bind(struct device *dev, ioasid_t pasid,
- struct arm_smmu_bond *bond;
- struct arm_smmu_master *master = dev_iommu_priv_get(dev);
- struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
-- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
-+ struct arm_smmu_domain *smmu_domain;
-+
-+ if (!(domain->type & __IOMMU_DOMAIN_PAGING))
-+ return -ENODEV;
-+ smmu_domain = to_smmu_domain(domain);
-+ if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1)
-+ return -ENODEV;
-
- if (!master || !master->sva_enabled)
- return -ENODEV;
---
-2.43.0
-
arm64-dts-rockchip-add-missing-interrupt-names-for-r.patch
arm64-dts-rockchip-fix-reset-names-for-rk356x-i2s2-c.patch
arm64-dts-rockchip-drop-rockchip-trcm-sync-tx-only-f.patch
-iommu-arm-smmu-v3-check-that-the-rid-domain-is-s1-in.patch
objtool-fix-unwind_hint_-save-restore-across-basic-b.patch
x86-relocs-ignore-relocations-in-.notes-section.patch
sunrpc-fix-a-memleak-in-gss_import_v2_context.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
