sim: riscv: Fix PC at gdb breakpoints

The uncompressed EBREAK instruction does not work
correctly this way, and the comment saying that
GDB expects us to step over EBREAK is just wrong.
The PC was always 4 bytes too high, which skips one
instruction at break and step over commands, and
causes complete chaos.  The compressed EBREAK was
already implemented correctly.

Tested by using gdb's "target sim" and single-stepping.

Approved-By: Andrew Burgess <aburgess@redhat.com>

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index adff99921c65fd2ede0a411572d0ee10ed0aa9f8..ddc7e1d3e98b472b337942fe9288478660447412 100644 (file)
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -623,9 +623,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_EBREAK:
       TRACE_INSN (cpu, "ebreak;");
-      /* GDB expects us to step over EBREAK.  */
-      sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc + 4, sim_stopped,
-                      SIM_SIGTRAP);
+      sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped, SIM_SIGTRAP);
       break;
     case MATCH_ECALL:
       TRACE_INSN (cpu, "ecall;");