drm/i915/ddi: write payload for 128b/132b SST

Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
start from slot 0, with dp_m_n.tu slots.

This is preparation for enabling 128b/132b SST. This path is not
reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.

v2: Handle drm_dp_dpcd_write_payload() failures (Imre)

v3: Include drm_dp_helper.h (kernel test robot)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250107095414.1244286-1-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 44f9bde2cdcc361e5391e889aa7246f64231cc52..f8e111d8c3a5433259b657105bc8b14e9765f8ec 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -28,6 +28,7 @@
 #include <linux/iopoll.h>
 #include <linux/string_helpers.h>
 
+#include <drm/display/drm_dp_helper.h>
 #include <drm/display/drm_scdc_helper.h>
 #include <drm/drm_privacy_screen_consumer.h>
 
@@ -2574,6 +2575,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 {
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+       int ret;
 
        intel_dp_set_link_params(intel_dp,
                                 crtc_state->port_clock,
@@ -2668,6 +2670,14 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
        /* 6.o Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
 
+       /* 7.a 128b/132b SST. */
+       if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
+               /* VCPID 1, start slot 0 for 128b/132b, tu slots */
+               ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
+               if (ret < 0)
+                       intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
+       }
+
        if (!is_mst)
                intel_dsc_dp_pps_write(encoder, crtc_state);
 }
@@ -2681,6 +2691,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
        bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+       int ret;
 
        intel_dp_set_link_params(intel_dp,
                                 crtc_state->port_clock,
@@ -2807,6 +2818,13 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
        /* 7.l Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
 
+       if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
+               /* VCPID 1, start slot 0 for 128b/132b, tu slots */
+               ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
+               if (ret < 0)
+                       intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
+       }
+
        if (!is_mst)
                intel_dsc_dp_pps_write(encoder, crtc_state);
 }