arm64: dts: ti: k3-am62a: add opp frequencies

One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)

The OPPs available for the Cortex-A53s on the AM62Ax can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
to only OPP entries the variant supports. A table of all these variants
can be found in it's data sheet[0] for the AM62Ax family.

Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.

[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-2-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
index f5ac101a04dfa0bdae8ac4f43b01473725433c51..0b1dd5390cd3f42b0ec56bab042388722b4c22a1 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
@@ -17,6 +17,11 @@
                        reg = <0x14 0x4>;
                };
 
+               opp_efuse_table: syscon@18 {
+                       compatible = "ti,am62-opp-efuse-table", "syscon";
+                       reg = <0x18 0x4>;
+               };
+
                cpsw_mac_syscon: ethernet-mac-syscon@200 {
                        compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
                        reg = <0x200 0x8>;

diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
index f86a23404e6dde3ca90e41ac0efdb378948e6d50..6c99221beb6bd8e5ad93888e6b659cc6e08fb679 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
@@ -48,6 +48,8 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&L2_0>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       clocks = <&k3_clks 135 0>;
                };
 
                cpu1: cpu@1 {
@@ -62,6 +64,8 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&L2_0>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       clocks = <&k3_clks 136 0>;
                };
 
                cpu2: cpu@2 {
@@ -76,6 +80,8 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&L2_0>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       clocks = <&k3_clks 137 0>;
                };
 
                cpu3: cpu@3 {
@@ -90,6 +96,51 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&L2_0>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       clocks = <&k3_clks 138 0>;
+               };
+       };
+
+       a53_opp_table: opp-table {
+               compatible = "operating-points-v2-ti-cpu";
+               opp-shared;
+               syscon = <&opp_efuse_table>;
+
+               opp-200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-supported-hw = <0x01 0x0007>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-supported-hw = <0x01 0x0007>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-supported-hw = <0x01 0x0007>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-supported-hw = <0x01 0x0007>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-supported-hw = <0x01 0x0006>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-1250000000 {
+                       opp-hz = /bits/ 64 <1250000000>;
+                       opp-supported-hw = <0x01 0x0004>;
+                       clock-latency-ns = <6000000>;
+                       opp-suspend;
                };
        };