riscv: dts: thead: add xtheadvector to the th1520 devicetree

The th1520 support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/
Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index e680d1a7c821f381d116748ed063fe2649aedaca..0b57699ba398d596ffe1feb330ed21589a6e42f4 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -25,7 +25,8 @@
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm";
+                                              "zifencei", "zihpm", "xtheadvector";
+                       thead,vlenb = <16>;
                        reg = <0>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
@@ -49,7 +50,8 @@
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm";
+                                              "zifencei", "zihpm", "xtheadvector";
+                       thead,vlenb = <16>;
                        reg = <1>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
@@ -73,7 +75,8 @@
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm";
+                                              "zifencei", "zihpm", "xtheadvector";
+                       thead,vlenb = <16>;
                        reg = <2>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
@@ -97,7 +100,8 @@
                        riscv,isa = "rv64imafdc";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm";
+                                              "zifencei", "zihpm", "xtheadvector";
+                       thead,vlenb = <16>;
                        reg = <3>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;