arm64: dts: qcom: qdu1000: Fix LLCC reg property

The LLCC binding and driver was corrected to handle the stride
varying between platforms. Switch to the new format to ensure
accesses are done in the right place.

Fixes: b0e0290bc47d ("arm64: dts: qcom: qdu1000: correct LLCC reg entries")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240619061641.5261-2-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index f2a5e2e40461fec72262e7d0b9957bafdb96ca67..f90f03fa6a24fc0a8159c9b36635c32b7ef69495 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1459,9 +1459,23 @@
 
                system-cache-controller@19200000 {
                        compatible = "qcom,qdu1000-llcc";
-                       reg = <0 0x19200000 0 0xd80000>,
+                       reg = <0 0x19200000 0 0x80000>,
+                             <0 0x19300000 0 0x80000>,
+                             <0 0x19600000 0 0x80000>,
+                             <0 0x19700000 0 0x80000>,
+                             <0 0x19a00000 0 0x80000>,
+                             <0 0x19b00000 0 0x80000>,
+                             <0 0x19e00000 0 0x80000>,
+                             <0 0x19f00000 0 0x80000>,
                              <0 0x1a200000 0 0x80000>;
                        reg-names = "llcc0_base",
+                                   "llcc1_base",
+                                   "llcc2_base",
+                                   "llcc3_base",
+                                   "llcc4_base",
+                                   "llcc5_base",
+                                   "llcc6_base",
+                                   "llcc7_base",
                                    "llcc_broadcast_base";
                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
                };