drop some 4.19, 5.4, and 5.10 patches

diff --git a/queue-4.19/drm-amdgpu-fix-build_coefficients-argument.patch b/queue-4.19/drm-amdgpu-fix-build_coefficients-argument.patch
deleted file mode 100644 (file)
index c2645c3..0000000
--- a/queue-4.19/drm-amdgpu-fix-build_coefficients-argument.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 7c9a300f59db519c4684e90eb9faac370b8e0271 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 26 Oct 2020 22:00:32 +0100
-Subject: drm/amdgpu: fix build_coefficients() argument
-
-From: Arnd Bergmann <arnd@arndb.de>
-
-[ Upstream commit dbb60031dd0c2b85f10ce4c12ae604c28d3aaca4 ]
-
-gcc -Wextra warns about a function taking an enum argument
-being called with a bool:
-
-drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c: In function 'apply_degamma_for_user_regamma':
-drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1617:29: warning: implicit conversion from 'enum <anonymous>' to 'enum dc_transfer_func_predefined' [-Wenum-conversion]
- 1617 |  build_coefficients(&coeff, true);
-
-It appears that a patch was added using the old calling conventions
-after the type was changed, and the value should actually be 0
-(TRANSFER_FUNCTION_SRGB) here instead of 1 (true).
-
-Fixes: 55a01d4023ce ("drm/amd/display: Add user_regamma to color module")
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
-index 11ea1a0e629bd..458e82da3c85b 100644
---- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
-+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
-@@ -1296,7 +1296,7 @@ static void apply_degamma_for_user_regamma(struct pwl_float_data_ex *rgb_regamma
-       struct pwl_float_data_ex *rgb = rgb_regamma;
-       const struct hw_x_point *coord_x = coordinates_x;
- 
--      build_coefficients(&coeff, true);
-+      build_coefficients(&coeff, TRANSFER_FUNCTION_SRGB);
- 
-       i = 0;
-       while (i != hw_points_num + 1) {
--- 
-2.27.0
-

diff --git a/queue-4.19/series b/queue-4.19/series
index 4c8b12348e86e357b8c2300a21b59d396c8b18bf..48c5852864fb6d7b28a4fdf5e8143f872af9a2a9 100644 (file)
--- a/queue-4.19/series
+++ b/queue-4.19/series
@@ -112,7 +112,6 @@ sched-reenable-interrupts-in-do_sched_yield.patch
 crypto-talitos-endianess-in-current_desc_hdr.patch
 crypto-talitos-fix-return-type-of-current_desc_hdr.patch
 crypto-inside-secure-fix-sizeof-mismatch.patch
-drm-amdgpu-fix-build_coefficients-argument.patch
 powerpc-64-set-up-a-kernel-stack-for-secondaries-bef.patch
 spi-img-spfi-fix-reference-leak-in-img_spfi_resume.patch
 drm-msm-dsi_pll_10nm-restore-vco-rate-during-restore.patch

diff --git a/queue-5.10/drm-amd-display-honor-the-offset-for-plane-0.patch b/queue-5.10/drm-amd-display-honor-the-offset-for-plane-0.patch
deleted file mode 100644 (file)
index 8b509d4..0000000
--- a/queue-5.10/drm-amd-display-honor-the-offset-for-plane-0.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From be7b9b327e79cd2db07b659af599867b629b2f66 Mon Sep 17 00:00:00 2001
-From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-Date: Sat, 21 Dec 2019 19:05:37 +0100
-Subject: drm/amd/display: Honor the offset for plane 0.
-
-From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-
-commit be7b9b327e79cd2db07b659af599867b629b2f66 upstream.
-
-With modifiers I'd like to support non-dedicated buffers for
-images.
-
-Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
-Cc: stable@vger.kernel.org # 5.1.0
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   14 +++++++++-----
- 1 file changed, 9 insertions(+), 5 deletions(-)
-
---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-@@ -3746,6 +3746,7 @@ fill_plane_dcc_attributes(struct amdgpu_
-       struct dc *dc = adev->dm.dc;
-       struct dc_dcc_surface_param input;
-       struct dc_surface_dcc_cap output;
-+      uint64_t plane_address = afb->address + afb->base.offsets[0];
-       uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
-       uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
-       uint64_t dcc_address;
-@@ -3789,7 +3790,7 @@ fill_plane_dcc_attributes(struct amdgpu_
-               AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
-       dcc->independent_64b_blks = i64b;
- 
--      dcc_address = get_dcc_address(afb->address, info);
-+      dcc_address = get_dcc_address(plane_address, info);
-       address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
-       address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
- 
-@@ -3820,6 +3821,8 @@ fill_plane_buffer_attributes(struct amdg
-       address->tmz_surface = tmz_surface;
- 
-       if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+              uint64_t addr = afb->address + fb->offsets[0];
-+
-               plane_size->surface_size.x = 0;
-               plane_size->surface_size.y = 0;
-               plane_size->surface_size.width = fb->width;
-@@ -3828,9 +3831,10 @@ fill_plane_buffer_attributes(struct amdg
-                       fb->pitches[0] / fb->format->cpp[0];
- 
-               address->type = PLN_ADDR_TYPE_GRAPHICS;
--              address->grph.addr.low_part = lower_32_bits(afb->address);
--              address->grph.addr.high_part = upper_32_bits(afb->address);
-+              address->grph.addr.low_part = lower_32_bits(addr);
-+              address->grph.addr.high_part = upper_32_bits(addr);
-       } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
-+              uint64_t luma_addr = afb->address + fb->offsets[0];
-               uint64_t chroma_addr = afb->address + fb->offsets[1];
- 
-               plane_size->surface_size.x = 0;
-@@ -3851,9 +3855,9 @@ fill_plane_buffer_attributes(struct amdg
- 
-               address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
-               address->video_progressive.luma_addr.low_part =
--                      lower_32_bits(afb->address);
-+                      lower_32_bits(luma_addr);
-               address->video_progressive.luma_addr.high_part =
--                      upper_32_bits(afb->address);
-+                      upper_32_bits(luma_addr);
-               address->video_progressive.chroma_addr.low_part =
-                       lower_32_bits(chroma_addr);
-               address->video_progressive.chroma_addr.high_part =

diff --git a/queue-5.10/series b/queue-5.10/series
index 6a2b4ba01ea74b1ab2e03df4cadc371ab2253009..c9b2ee7fec5e53c7b448075d1cbdf62b5447332b 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -629,7 +629,6 @@ fsnotify-fix-events-reported-to-watching-parent-and-child.patch
 jfs-fix-array-index-bounds-check-in-dbadjtree.patch
 drm-panfrost-fix-job-timeout-handling.patch
 drm-panfrost-move-the-gpu-reset-bits-outside-the-timeout-handler.patch
-drm-amd-display-honor-the-offset-for-plane-0.patch
 drm-amdgpu-only-set-dp-subconnector-type-on-dp-and-edp-connectors.patch
 drm-amd-display-fix-memory-leaks-in-s3-resume.patch
 drm-dp_aux_dev-check-aux_dev-before-use-in-drm_dp_aux_dev_get_by_minor.patch

diff --git a/queue-5.4/drm-amd-display-honor-the-offset-for-plane-0.patch b/queue-5.4/drm-amd-display-honor-the-offset-for-plane-0.patch
deleted file mode 100644 (file)
index 830eecd..0000000
--- a/queue-5.4/drm-amd-display-honor-the-offset-for-plane-0.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From be7b9b327e79cd2db07b659af599867b629b2f66 Mon Sep 17 00:00:00 2001
-From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-Date: Sat, 21 Dec 2019 19:05:37 +0100
-Subject: drm/amd/display: Honor the offset for plane 0.
-
-From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-
-commit be7b9b327e79cd2db07b659af599867b629b2f66 upstream.
-
-With modifiers I'd like to support non-dedicated buffers for
-images.
-
-Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
-Cc: stable@vger.kernel.org # 5.1.0
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   14 +++++++++-----
- 1 file changed, 9 insertions(+), 5 deletions(-)
-
---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-@@ -2720,6 +2720,7 @@ fill_plane_dcc_attributes(struct amdgpu_
-       struct dc *dc = adev->dm.dc;
-       struct dc_dcc_surface_param input;
-       struct dc_surface_dcc_cap output;
-+      uint64_t plane_address = afb->address + afb->base.offsets[0];
-       uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
-       uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
-       uint64_t dcc_address;
-@@ -2763,7 +2764,7 @@ fill_plane_dcc_attributes(struct amdgpu_
-               AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
-       dcc->independent_64b_blks = i64b;
- 
--      dcc_address = get_dcc_address(afb->address, info);
-+      dcc_address = get_dcc_address(plane_address, info);
-       address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
-       address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
- 
-@@ -2791,6 +2792,8 @@ fill_plane_buffer_attributes(struct amdg
-       memset(address, 0, sizeof(*address));
- 
-       if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+              uint64_t addr = afb->address + fb->offsets[0];
-+
-               plane_size->surface_size.x = 0;
-               plane_size->surface_size.y = 0;
-               plane_size->surface_size.width = fb->width;
-@@ -2799,9 +2802,10 @@ fill_plane_buffer_attributes(struct amdg
-                       fb->pitches[0] / fb->format->cpp[0];
- 
-               address->type = PLN_ADDR_TYPE_GRAPHICS;
--              address->grph.addr.low_part = lower_32_bits(afb->address);
--              address->grph.addr.high_part = upper_32_bits(afb->address);
-+              address->grph.addr.low_part = lower_32_bits(addr);
-+              address->grph.addr.high_part = upper_32_bits(addr);
-       } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
-+              uint64_t luma_addr = afb->address + fb->offsets[0];
-               uint64_t chroma_addr = afb->address + fb->offsets[1];
- 
-               plane_size->surface_size.x = 0;
-@@ -2822,9 +2826,9 @@ fill_plane_buffer_attributes(struct amdg
- 
-               address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
-               address->video_progressive.luma_addr.low_part =
--                      lower_32_bits(afb->address);
-+                      lower_32_bits(luma_addr);
-               address->video_progressive.luma_addr.high_part =
--                      upper_32_bits(afb->address);
-+                      upper_32_bits(luma_addr);
-               address->video_progressive.chroma_addr.low_part =
-                       lower_32_bits(chroma_addr);
-               address->video_progressive.chroma_addr.high_part =

diff --git a/queue-5.4/series b/queue-5.4/series
index 3b39939582f54905019a5066b7f64142b54bf53f..764bde82c03ccfe02b18d0bbde8cc9ec98b828e5 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -390,7 +390,6 @@ ubifs-wbuf-don-t-leak-kernel-memory-to-flash.patch
 jffs2-fix-gc-exit-abnormally.patch
 jffs2-fix-ignoring-mounting-options-problem-during-remounting.patch
 jfs-fix-array-index-bounds-check-in-dbadjtree.patch
-drm-amd-display-honor-the-offset-for-plane-0.patch
 drm-amd-display-fix-memory-leaks-in-s3-resume.patch
 drm-dp_aux_dev-check-aux_dev-before-use-in-drm_dp_aux_dev_get_by_minor.patch
 drm-i915-fix-mismatch-between-misplaced-vma-check-and-vma-insert.patch