--- /dev/null
+From 6cbcf596934c8e16d6288c7cc62dfb7ad8eadf15 Mon Sep 17 00:00:00 2001
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+Date: Fri, 22 Mar 2019 17:50:15 +0200
+Subject: xhci: Fix port resume done detection for SS ports with LPM enabled
+
+From: Mathias Nyman <mathias.nyman@linux.intel.com>
+
+commit 6cbcf596934c8e16d6288c7cc62dfb7ad8eadf15 upstream.
+
+A suspended SS port in U3 link state will go to U0 when resumed, but
+can almost immediately after that enter U1 or U2 link power save
+states before host controller driver reads the port status.
+
+Host controller driver only checks for U0 state, and might miss
+the finished resume, leaving flags unclear and skip notifying usb
+code of the wake.
+
+Add U1 and U2 to the possible link states when checking for finished
+port resume.
+
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+
+---
+ drivers/usb/host/xhci-ring.c | 9 ++++++---
+ drivers/usb/host/xhci.h | 1 +
+ 2 files changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -1599,10 +1599,13 @@ static void handle_port_status(struct xh
+ }
+ }
+
+- if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
+- DEV_SUPERSPEED(temp)) {
++ if ((temp & PORT_PLC) &&
++ DEV_SUPERSPEED(temp) &&
++ ((temp & PORT_PLS_MASK) == XDEV_U0 ||
++ (temp & PORT_PLS_MASK) == XDEV_U1 ||
++ (temp & PORT_PLS_MASK) == XDEV_U2)) {
+ xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
+- /* We've just brought the device into U0 through either the
++ /* We've just brought the device into U0/1/2 through either the
+ * Resume state after a device remote wakeup, or through the
+ * U3Exit state after a host-initiated resume. If it's a device
+ * initiated remote wake, don't pass up the link state change,
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -283,6 +283,7 @@ struct xhci_op_regs {
+ */
+ #define PORT_PLS_MASK (0xf << 5)
+ #define XDEV_U0 (0x0 << 5)
++#define XDEV_U1 (0x1 << 5)
+ #define XDEV_U2 (0x2 << 5)
+ #define XDEV_U3 (0x3 << 5)
+ #define XDEV_RESUME (0xf << 5)