--- /dev/null
+From d14f0f391370ca45abc208a13c5863a9d05f422c Mon Sep 17 00:00:00 2001
+From: Prathyushi Nangia <prathyushi.nangia@amd.com>
+Date: Tue, 9 Dec 2025 10:01:33 -0600
+Subject: x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op cache
+
+From: Prathyushi Nangia <prathyushi.nangia@amd.com>
+
+commit c21b90f77687075115d989e53a8ec5e2bb427ab1 upstream.
+
+Make sure resources are not improperly shared in the op cache and
+cause instruction corruption this way.
+
+Signed-off-by: Prathyushi Nangia <prathyushi.nangia@amd.com>
+Co-developed-by: Borislav Petkov (AMD) <bp@alien8.de>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/include/asm/msr-index.h | 1 +
+ arch/x86/kernel/cpu/amd.c | 3 +++
+ tools/arch/x86/include/asm/msr-index.h | 3 +++
+ 3 files changed, 7 insertions(+)
+
+diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
+index 390db709b432..59bee2206d97 100644
+--- a/arch/x86/include/asm/msr-index.h
++++ b/arch/x86/include/asm/msr-index.h
+@@ -570,6 +570,7 @@
+ /* Zen4 */
+ #define MSR_ZEN4_BP_CFG 0xc001102e
+ #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
++#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33
+
+ /* Zen 2 */
+ #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
+diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
+index 3a446f2b6d30..519e388083b2 100644
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -1197,6 +1197,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
+ {
+ init_amd_zen_common();
+ init_spectral_chicken(c);
++
++ if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
++ msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT);
+ }
+
+ static void init_amd_zen3(struct cpuinfo_x86 *c)
+diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
+index 8fb925676813..c28d75fe4dee 100644
+--- a/tools/arch/x86/include/asm/msr-index.h
++++ b/tools/arch/x86/include/asm/msr-index.h
+@@ -523,6 +523,9 @@
+
+ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
+
++#define MSR_ZEN4_BP_CFG 0xc001102e
++#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33
++
+ /* Fam 17h MSRs */
+ #define MSR_F17H_IRPERF 0xc00000e9
+
+--
+2.51.0
+