x86/cpufeatures: Add X86_FEATURE_APX

Intel Advanced Performance Extensions (APX) introduce a new set of
general-purpose registers, managed as an extended state component via the
xstate management facility.

Before enabling this new xstate, define a feature flag to clarify the
dependency in xsave_cpuid_features[]. APX is enumerated under CPUID level
7 with EDX=1. Since this CPUID leaf is not yet allocated, place the flag
in a scattered feature word.

While this feature is intended only for userspace, exposing it via
/proc/cpuinfo is unnecessary. Instead, the existing arch_prctl(2)
mechanism with the ARCH_GET_XCOMP_SUPP option can be used to query the
feature availability.

Finally, clarify that APX depends on XSAVE.

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: https://lore.kernel.org/r/20250416021720.12305-2-chang.seok.bae@intel.com

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index bc81b9d1aeca5c0cbe62ea3c48147238bacce74c..478ab362fda2066950280136854d18a02121fbf5 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -481,6 +481,7 @@
 #define X86_FEATURE_AMD_HTR_CORES      (21*32+ 6) /* Heterogeneous Core Topology */
 #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32+ 7) /* Workload Classification */
 #define X86_FEATURE_PREFER_YMM         (21*32+ 8) /* Avoid ZMM registers due to downclocking */
+#define X86_FEATURE_APX                        (21*32+ 9) /* Advanced Performance Extensions */
 
 /*
  * BUG word(s)

diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index 94c062cddfa4e7384937c2951a2824b2409205d5..46efcbd6afa41ce8201229612fc082a3f3760868 100644 (file)
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -28,6 +28,7 @@ static const struct cpuid_dep cpuid_deps[] = {
        { X86_FEATURE_PKU,                      X86_FEATURE_XSAVE     },
        { X86_FEATURE_MPX,                      X86_FEATURE_XSAVE     },
        { X86_FEATURE_XGETBV1,                  X86_FEATURE_XSAVE     },
+       { X86_FEATURE_APX,                      X86_FEATURE_XSAVE     },
        { X86_FEATURE_CMOV,                     X86_FEATURE_FXSR      },
        { X86_FEATURE_MMX,                      X86_FEATURE_FXSR      },
        { X86_FEATURE_MMXEXT,                   X86_FEATURE_MMX       },

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index c75c57b32b742d30f725d61694a81a1d3737396a..dbf6d71bdf18b48154cd4788843dddab091f9080 100644 (file)
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = {
        { X86_FEATURE_APERFMPERF,               CPUID_ECX,  0, 0x00000006, 0 },
        { X86_FEATURE_EPB,                      CPUID_ECX,  3, 0x00000006, 0 },
        { X86_FEATURE_INTEL_PPIN,               CPUID_EBX,  0, 0x00000007, 1 },
+       { X86_FEATURE_APX,                      CPUID_EDX, 21, 0x00000007, 1 },
        { X86_FEATURE_RRSBA_CTRL,               CPUID_EDX,  2, 0x00000007, 2 },
        { X86_FEATURE_BHI_CTRL,                 CPUID_EDX,  4, 0x00000007, 2 },
        { X86_FEATURE_CQM_LLC,                  CPUID_EDX,  1, 0x0000000f, 0 },