arm64: dts: qcom: x1e80100-crd: enable SDX65 modem

Enable PCIe5 and the SDX65 modem.

Note that the modem may need to be flashed with firmware before use.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240722094249.26471-9-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index b415c8b7c89bca01b2e34c63a3babd9d1cfa1485..8c9f6720a33eb1c47adc117610b9517a659c26a6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -302,6 +302,22 @@
                pinctrl-names = "default";
                pinctrl-0 = <&nvme_reg_en>;
        };
+
+       vreg_wwan: regulator-wwan {
+               compatible = "regulator-fixed";
+
+               regulator-name = "SDX_VPH_PWR";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+
+               pinctrl-0 = <&wwan_sw_en>;
+               pinctrl-names = "default";
+
+               regulator-boot-on;
+       };
 };
 
 &apps_rsc {
@@ -789,6 +805,25 @@
        status = "okay";
 };
 
+&pcie5 {
+       perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+
+       vddpe-3v3-supply = <&vreg_wwan>;
+
+       pinctrl-0 = <&pcie5_default>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie5_phy {
+       vdda-phy-supply = <&vreg_l3i_0p8>;
+       vdda-pll-supply = <&vreg_l3e_1p2>;
+
+       status = "okay";
+};
+
 &pcie6a {
        perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
        wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
@@ -987,6 +1022,29 @@
                };
        };
 
+       pcie5_default: pcie5-default-state {
+               clkreq-n-pins {
+                       pins = "gpio150";
+                       function = "pcie5_clk";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio149";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-disable;
+               };
+
+               wake-n-pins {
+                       pins = "gpio151";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
        pcie6a_default: pcie6a-default-state {
                clkreq-n-pins {
                        pins = "gpio153";
@@ -1038,6 +1096,13 @@
                bias-disable;
                output-low;
        };
+
+       wwan_sw_en: wwan-sw-en-state {
+               pins = "gpio221";
+               function = "gpio";
+               drive-strength = <4>;
+               bias-disable;
+       };
 };
 
 &uart21 {