arm64: dts: qcom: sc8280xp: Fix interrupt type of camss interrupts

Qualcomm IP catalog says that all CAMSS interrupts are edge rising,
fix it in the CAMSS device tree node for sc8280xp SoC.

Fixes: 5994dd60753e ("arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241127122950.885982-5-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 276b46a1693355577d3f3986c9f0da1f53012272..01501acb1790a100cb14e2d3e7a461159b3d0531 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3906,26 +3906,26 @@
                                    "vfe3",
                                    "csid3";
 
-                       interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
                        interrupt-names = "csid1_lite",
                                          "vfe_lite1",
                                          "csiphy3",