[AArch64] Add HF vector modes to lane-to-lane INS pattern

        * config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
        Use VALL_F16 iterator rather than VALL.

        * gcc.target/aarch64/hfmode_ins_1.c: New test.

From-SVN: r248835

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 345c3ecdc893f2bd5abb523d84bace104fe532a2..079f1fd61f091760f0c50dbba36b3ee7f9a3870d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -8,6 +8,11 @@
 
        * config/vx-common.h (DWARF_UNWIND_INFO): Switch #define to 1.
 
+2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
+       Use VALL_F16 iterator rather than VALL.
+
 2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/aarch64/aarch64.c (aarch64_split_compare_and_swap):

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 6852f39c35aec7a482c1a841118131baf9db7c0f..693b476788e94e9b43a40944d66e0693307cea8d 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -565,14 +565,14 @@
 )
 
 (define_insn "*aarch64_simd_vec_copy_lane<mode>"
-  [(set (match_operand:VALL 0 "register_operand" "=w")
-       (vec_merge:VALL
-           (vec_duplicate:VALL
+  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
+       (vec_merge:VALL_F16
+           (vec_duplicate:VALL_F16
              (vec_select:<VEL>
-               (match_operand:VALL 3 "register_operand" "w")
+               (match_operand:VALL_F16 3 "register_operand" "w")
                (parallel
                  [(match_operand:SI 4 "immediate_operand" "i")])))
-           (match_operand:VALL 1 "register_operand" "0")
+           (match_operand:VALL_F16 1 "register_operand" "0")
            (match_operand:SI 2 "immediate_operand" "i")))]
   "TARGET_SIMD"
   {

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fdd4a90ddca5ab8733c8b44ede504dc7bba865ed..70a8335d5df66e4a16b32d414ff81376858ca2aa 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -6,6 +6,10 @@
        * gcc.target/powerpc/fold-vec-minmax-longlong.c: New.
        * gcc.target/powerpc/fold-vec-minmax-short.c: New.
 
+2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/aarch64/hfmode_ins_1.c: New test.
+
 2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c b/gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c
new file mode 100644 (file)
index 0000000..7fafe92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check that we can perform this in a single INS without doing any DUPs.  */
+
+#include <arm_neon.h>
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b)
+{
+  return vsetq_lane_f16 (vgetq_lane_f16 (b, 2), a, 3);
+}
+
+float16x4_t
+bar (float16x4_t a, float16x4_t b)
+{
+  return vset_lane_f16 (vget_lane_f16 (b, 2), a, 3);
+}
+
+/* { dg-final { scan-assembler-times "ins\\t" 2 } } */
+/* { dg-final { scan-assembler-not "dup\\t" } } */