amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
        amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
                                 PACKET3_RELEASE_MEM_GCR_GL2_WB |
-                                PACKET3_RELEASE_MEM_GCR_GL2_INV |
-                                PACKET3_RELEASE_MEM_GCR_GL2_US |
-                                PACKET3_RELEASE_MEM_GCR_GL1_INV |
-                                PACKET3_RELEASE_MEM_GCR_GLV_INV |
-                                PACKET3_RELEASE_MEM_GCR_GLM_INV |
+                                PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
                                 PACKET3_RELEASE_MEM_GCR_GLM_WB |
                                 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
                                 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |