fsl_lpspi->rx(fsl_lpspi);
}
-static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
- struct spi_device *spi)
+static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
{
u32 temp = 0;
}
}
- if (spi->mode & SPI_CPOL)
+ if (fsl_lpspi->config.mode & SPI_CPOL)
temp |= TCR_CPOL;
- if (spi->mode & SPI_CPHA)
+ if (fsl_lpspi->config.mode & SPI_CPHA)
temp |= TCR_CPHA;
writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
if (ret < 0)
return ret;
- fsl_lpspi_set_cmd(fsl_lpspi, spi);
+ fsl_lpspi_set_cmd(fsl_lpspi);
/* No IRQs */
writel(0, fsl_lpspi->base + IMX7ULP_IER);
t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz;
- fsl_lpspi_set_cmd(fsl_lpspi, spi);
+ fsl_lpspi_set_cmd(fsl_lpspi);
fsl_lpspi->is_first_byte = false;
if (fsl_lpspi->usedma)