]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm: dts: arm: Drop redundant fixed-factor clocks
authorRob Herring <robh@kernel.org>
Thu, 27 Jun 2024 19:57:38 +0000 (21:57 +0200)
committerArnd Bergmann <arnd@arndb.de>
Fri, 28 Jun 2024 15:28:45 +0000 (17:28 +0200)
There's not much reason to have multiple fixed-factor-clock instances
which are all the same factor and clock input. Drop the nodes, but keep
the labels to minimize the changes and keep some distinction of the
different clocks.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20240528191536.1444649-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240627-arm-dts-fixes-v1-1-40a2cb7d344b@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/boot/dts/arm/arm-realview-eb.dtsi
arch/arm/boot/dts/arm/arm-realview-pb1176.dts
arch/arm/boot/dts/arm/arm-realview-pb11mp.dts
arch/arm/boot/dts/arm/arm-realview-pbx.dtsi
arch/arm/boot/dts/arm/integratorap.dts
arch/arm/boot/dts/arm/mps2.dtsi

index fbb2258b451f904856d6fedd41af6e67afeea5ad..ed3ed5a4f0f78d96ae89c389cc5cf3858a97ced9 100644 (file)
@@ -53,7 +53,7 @@
                regulator-boot-on;
         };
 
-       xtal24mhz: xtal24mhz@24M {
+       xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <24000000>;
                clocks = <&xtal24mhz>;
        };
 
-       mclk: mclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       kmiclk: kmiclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       sspclk: sspclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       uartclk: uartclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       wdogclk: wdogclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
        /* FIXME: this actually hangs off the PLL clocks */
        pclk: pclk@0 {
                #clock-cells = <0>;
index d99bac02232b3703a04b8d03f36cf5eb12bd9f4e..ab2c9b71da69ee83e8a47527488a604f0b79101e 100644 (file)
@@ -63,7 +63,7 @@
                regulator-boot-on;
        };
 
-       xtal24mhz: xtal24mhz@24M {
+       xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <24000000>;
                clocks = <&xtal24mhz>;
        };
 
-       mclk: mclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       kmiclk: kmiclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       sspclk: sspclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       uartclk: uartclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
        /* FIXME: this actually hangs off the PLL clocks */
        pclk: pclk@0 {
                #clock-cells = <0>;
index 89103d54ecc15c9afbdca380ab01b9427924cc9c..a4c2d96aa5c8127062868f9035896af2fca9fbbe 100644 (file)
                regulator-boot-on;
        };
 
-       xtal24mhz: xtal24mhz@24M {
+       xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <24000000>;
                clocks = <&xtal24mhz>;
        };
 
-       mclk: mclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       kmiclk: kmiclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       sspclk: sspclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       uartclk: uartclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       wdogclk: wdogclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
        /* FIXME: this actually hangs off the PLL clocks */
        pclk: pclk@0 {
                #clock-cells = <0>;
index ec1507c5147c64ea978e133b5bc6bafc5238fa69..61dbe041c69b33322297398276e0f070673afd69 100644 (file)
@@ -62,7 +62,7 @@
                regulator-boot-on;
        };
 
-       xtal24mhz: xtal24mhz@24M {
+       xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <24000000>;
                clocks = <&xtal24mhz>;
        };
 
-       mclk: mclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       kmiclk: kmiclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       sspclk: sspclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       uartclk: uartclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
-       wdogclk: wdogclk@24M {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
        /* FIXME: this actually hangs off the PLL clocks */
        pclk: pclk@0 {
                #clock-cells = <0>;
index d9927d3181dce88ade9eb738c7ba29bb004d1555..27498e0f93f688d5d7931749b98655ccdb029619 100644 (file)
        };
 
        /* 24 MHz chrystal on the Integrator/AP development board */
-       xtal24mhz: xtal24mhz@24M {
+       xtal24mhz: pclk: clock-24000000 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <24000000>;
        };
 
-       pclk: pclk@0 {
-               #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
-               clock-div = <1>;
-               clock-mult = <1>;
-               clocks = <&xtal24mhz>;
-       };
-
        /* The UART clock is 14.74 MHz divided by an ICS525 */
        uartclk: uartclk@14.74M {
                #clock-cells = <0>;
index ce308820765b8e7105f5a4e321eec5df3107411a..d930168fbd918c1b3c2337b3fc833fdfb44fc700 100644 (file)
@@ -78,7 +78,7 @@
                clock-frequency = <75000000>;
        };
 
-       sysclk: clk-sys {
+       sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys {
                compatible = "fixed-factor-clock";
                clocks = <&oscclk0>;
                #clock-cells = <0>;
                clock-mult = <1>;
        };
 
-       spiclcd: clk-cpiclcd {
-               compatible = "fixed-factor-clock";
-               clocks = <&oscclk0>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };
-
-       spicon: clk-spicon {
-               compatible = "fixed-factor-clock";
-               clocks = <&oscclk0>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };
-
-       i2cclcd: clk-i2cclcd {
-               compatible = "fixed-factor-clock";
-               clocks = <&oscclk0>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };
-
-       i2caud: clk-i2caud {
-               compatible = "fixed-factor-clock";
-               clocks = <&oscclk0>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };
-
        soc {
                compatible = "simple-bus";
                ranges;