regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- wdogclk: wdogclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- wdogclk: wdogclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- wdogclk: wdogclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;
};
/* 24 MHz chrystal on the Integrator/AP development board */
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: pclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
- pclk: pclk@0 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* The UART clock is 14.74 MHz divided by an ICS525 */
uartclk: uartclk@14.74M {
#clock-cells = <0>;
clock-frequency = <75000000>;
};
- sysclk: clk-sys {
+ sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
clock-mult = <1>;
};
- spiclcd: clk-cpiclcd {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- spicon: clk-spicon {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- i2cclcd: clk-i2cclcd {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- i2caud: clk-i2caud {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
soc {
compatible = "simple-bus";
ranges;