drm/sun4i: Initialize registers in tcon-top driver

[ Upstream commit c96d62215fb540e2ae61de44cb7caf4db50958e3 ]

It turns out that TCON TOP registers in H6 SoC have non-zero reset
value. This may cause issues if bits are not changed during
configuration.

To prevent that, initialize registers to 0.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-24-jernej.skrabec@siol.net
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index 3040a79f298ffa2348b258c14a0307ee76fbd7ce..37158548b44761da124ca306e2a4ceb4fcca13c8 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -167,6 +167,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
                goto err_assert_reset;
        }
 
+       /*
+        * At least on H6, some registers have some bits set by default
+        * which may cause issues. Clear them here.
+        */
+       writel(0, regs + TCON_TOP_PORT_SEL_REG);
+       writel(0, regs + TCON_TOP_GATE_SRC_REG);
+
        /*
         * TCON TOP has two muxes, which select parent clock for each TCON TV
         * channel clock. Parent could be either TCON TV or TVE clock. For now