]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
6.18-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 25 Feb 2026 01:18:53 +0000 (17:18 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 25 Feb 2026 01:18:53 +0000 (17:18 -0800)
added patches:
net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch

queue-6.18/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch [new file with mode: 0644]
queue-6.18/series

diff --git a/queue-6.18/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch b/queue-6.18/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch
new file mode 100644 (file)
index 0000000..d495db9
--- /dev/null
@@ -0,0 +1,39 @@
+From e1aa5ef892fb4fa9014a25e87b64b97347919d37 Mon Sep 17 00:00:00 2001
+From: Huacai Chen <chenhuacai@loongson.cn>
+Date: Tue, 3 Feb 2026 14:29:01 +0800
+Subject: net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz
+
+From: Huacai Chen <chenhuacai@loongson.cn>
+
+commit e1aa5ef892fb4fa9014a25e87b64b97347919d37 upstream.
+
+Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
+and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
+Loongson STMMAC use 125MHz clocks and need 62 freq division to within
+2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
+to 100-150MHz, otherwise some PHYs may link fail.
+
+Cc: stable@vger.kernel.org
+Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson")
+Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
+Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
+Link: https://patch.msgid.link/20260203062901.2158236-1-chenhuacai@loongson.cn
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+@@ -90,8 +90,8 @@ static void loongson_default_data(struct
+       /* Get bus_id, this can be overwritten later */
+       plat->bus_id = pci_dev_id(pdev);
+-      /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
+-      plat->clk_csr = STMMAC_CSR_20_35M;
++      /* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
++      plat->clk_csr = STMMAC_CSR_100_150M;
+       plat->core_type = DWMAC_CORE_GMAC;
+       plat->force_sf_dma_mode = 1;
index e4a57d9608195aae4b833db35485bdb4428419d6..aafe84a1956e164bc94979ba49774c2ce5aea4b5 100644 (file)
@@ -638,3 +638,4 @@ drivers-hv-vmbus-use-kthread-for-vmbus-interrupts-on-preempt_rt.patch
 io_uring-rsrc-clean-up-buffer-cloning-arg-validation.patch
 selftests-bpf-test-bpf_skb_check_mtu-bpf_mtu_chk_segs-when-transport_header-is-not-set.patch
 drm-amd-display-clear-hdmi-hpd-pending-work-only-if-it-is-enabled.patch
+net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch