RISC-V: Fix failed tests for regression due to fix ICE patch

Ref:
https://github.com/ewlu/gcc-precommit-ci/issues/3096#issue-2854419069

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/bug-9.c: Added new failure check.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: Likewise.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
index 20ae9ebf6f22bf28964c8872f9020608bc794fc6..8cfe965887517228c3eb7d89cb27ae4fb5cf7ffc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
@@ -11,3 +11,4 @@ vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
index a064417169d86129cfbfe92c1465383366222b86..ebe31f5c961b81db6a387fce3e1bce85daaeed88 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
index 61d3fb25dc2d7a29e4e2a292e6fe95ba38b087f7..7e9a101795dcf16ebb33f292e9461d11b3730ad6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
index bfc26f8210ac8d0e7b1c853ea48d73abb94f26e7..b5354f4291f91f6f49718fc0b922f13fe4180e27 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
index 35a2924234f270957338c09020d762fc5ca84810..c1a574d5e294f30a36048894b89789c2889d2f17 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
index e3aef339d68da3975ab2c73365329f7e9a7530c6..62c2815fdad191ee631a4ffa8a0c9d92dcb41853 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
index b5a894ecad43abed8e38db8a0accc957baa685f1..f0b72e5060b2c5de7051f66a21961bac1f706938 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
index 7267fa3304b75c8227c0243ca2f6ea836790e40e..9f22a182d4ca588d1e541c608e05d2a4bf7488c0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
index 5a7c4481a5a9c9ecbaab1e1e17cefa8c9646e19b..1006ad4af186c1cfa92c2c0d11d2fbb249ad9690 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
index f1241cb1771440e6a7d551580b733d63ca34275d..de36e4310b022bcfc15d9c389e5356863711b6e7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
index 2738a29d6736b6aaa760d5495ff53b0cd1858c99..f87f8c54c8de139c5be9e6da95425d6ddd6d9444 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
index 8610000b474043787f4e90a4ad0d2b62436d00a3..c5bc8511b677c7cbdc55ae6125402b9c9e7c950a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
index 7eaa6adab826ada236ba17fdc80ed2333825e27c..738d2e6274863d06dbdc3e9cf0ca1523c7880b8d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
index eb74e33299fa4df7b6458ee9e522df4e1ff7cc4c..f82ad41cd50e253f2b780523c4cfb95cc3190376 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
index 590343ddbfdeda13edcd0f28c73a2afa7a1b5cec..b9aceb83682fc68d025d2d8cc467ef3c8673e0e3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
@@ -11,3 +11,4 @@ test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint32m1_t' requires the V ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint32m1_t' requires the V ISA extension" "" { target { "riscv*-*-*" } } 0 } */