arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support

Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs.

Configure the MIIC converter in mode 0x6:
  Port 0 <-> ETHSW Port 0
  Port 1 <-> ETHSW Port 1
  Port 2 <-> GMAC2
  Port 3 <-> GMAC1

Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added
once the switch driver is available.

Configure the MIIC converters to map ports according to the selected
switching mode, with converters 0 and 1 mapped to switch ports and
converters 2 and 3 mapped to GMAC ports.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251110203926.692242-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 799c58afd6fed3510673b97db21007266b9e9199..b7706d0bc3aa150c31b56bd9dee131ef396f1c94 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -149,7 +149,77 @@
        status = "okay";
 };
 
+&mdio1_phy {
+       reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
+};
+
+&mdio2_phy {
+       /*
+        * PHY2 Reset Configuration:
+        *
+        * SW6[1] OFF; SW6[2] ON; SW6[3] OFF - use pin P17_5 for GMAC_RESETOUT2#
+        */
+       reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
+};
+
 &pinctrl {
+       /*
+        * GMAC2 Pin Configuration:
+        *
+        * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
+        * SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5
+        * for Ethernet port 2
+        */
+       gmac2_pins: gmac2-pins {
+               pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
+                        <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
+                        <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
+                        <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
+                        <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
+                        <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
+                        <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
+                        <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
+                        <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
+                        <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
+                        <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
+                        <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
+                        <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
+                        <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
+                        <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
+                        <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
+                        <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
+                        <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
+                        <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
+       };
+
+       /*
+        * GMAC1 Pin Configuration:
+        *
+        * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
+        * P35_0-P35_2 for Ethernet port 3
+        */
+       gmac1_pins: gmac1-pins {
+               pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
+                        <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
+                        <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
+                        <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
+                        <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
+                        <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
+                        <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
+                        <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
+                        <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
+                        <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
+                        <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
+                        <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
+                        <RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
+                        <RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
+                        <RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
+                        <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
+                        <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
+                        <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
+                        <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
+       };
+
        /*
         * I2C0 Pin Configuration:
         * ------------------------

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index d698b6368ee7c025e314014278d45b9863470908..17c0c79fbd96bdb72ce02f6ae616528bdead8cf4 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -186,7 +186,85 @@
        status = "okay";
 };
 
+&mdio1_phy {
+       /*
+        * PHY3 Reset Configuration:
+        *
+        * DSW12[5] OFF; DSW12[6] ON - use pin P03_2 for GMAC_RESETOUT3#
+        */
+       reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
+};
+
+&mdio2_phy {
+       /*
+        * PHY2 Reset Configuration:
+        *
+        * DSW8[1] ON; DSW8[2] OFF; DSW12[7] OFF; DSW12[8] ON - use pin
+        * P03_1 for GMAC_RESETOUT2#
+        */
+       reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
+};
+
 &pinctrl {
+       /*
+        * GMAC2 Pin Configuration:
+        *
+        * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
+        * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
+        * P31_2, P31_4 and P31_5 are used for Ethernet port 2
+        */
+       gmac2_pins: gmac2-pins {
+               pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
+                        <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
+                        <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
+                        <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
+                        <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
+                        <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
+                        <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
+                        <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
+                        <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
+                        <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
+                        <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
+                        <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
+                        <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
+                        <RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
+                        <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
+                        <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
+                        <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
+                        <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
+                        <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
+
+       };
+
+       /*
+        * GMAC2 Pin Configuration:
+        *
+        * DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6
+        * for Ethernet port 3
+        * DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3
+        */
+       gmac1_pins: gmac1-pins {
+               pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
+                        <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
+                        <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD0 */
+                        <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
+                        <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
+                        <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
+                        <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
+                        <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
+                        <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
+                        <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
+                        <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
+                        <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
+                        <RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
+                        <RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
+                        <RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
+                        <RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
+                        <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
+                        <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
+                        <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
+       };
+
        /*
         * I2C0 Pin Configuration:
         * ------------------------

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 924a38c6cb0ff7f794fdd2eb4357c3ee18b8959d..3eed1f3948e8eaf698cd82528384be3fb67ce5ca 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -7,10 +7,14 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/mscc-phy-vsc8531.h>
+#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
 #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
 
 / {
        aliases {
+               ethernet3 = &gmac1;
+               ethernet2 = &gmac2;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                mmc0 = &sdhi0;
@@ -70,10 +74,34 @@
        status = "okay";
 };
 
+&ethss {
+       status = "okay";
+
+       renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
+};
+
 &extal_clk {
        clock-frequency = <25000000>;
 };
 
+&gmac1 {
+       pinctrl-0 = <&gmac1_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&mdio1_phy>;
+       phy-mode = "rgmii-id";
+       pcs-handle = <&mii_conv3>;
+       status = "okay";
+};
+
+&gmac2 {
+       pinctrl-0 = <&gmac2_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&mdio2_phy>;
+       phy-mode = "rgmii-id";
+       pcs-handle = <&mii_conv2>;
+       status = "okay";
+};
+
 &hsusb {
        dr_mode = "otg";
        status = "okay";
@@ -87,6 +115,48 @@
        };
 };
 
+&mdio1 {
+       mdio1_phy: ethernet-phy@3 {
+               compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
+               reg = <3>;
+               vsc8531,led-0-mode = <VSC8531_ACTIVITY>;
+               vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+               reset-assert-us = <2000>;
+               reset-deassert-us = <15000>;
+       };
+};
+
+&mdio2 {
+       mdio2_phy: ethernet-phy@2 {
+               compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
+               reg = <2>;
+               vsc8531,led-0-mode = <VSC8531_ACTIVITY>;
+               vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+               reset-assert-us = <2000>;
+               reset-deassert-us = <15000>;
+       };
+};
+
+&mii_conv0 {
+       renesas,miic-input = <ETHSS_ETHSW_PORT0>;
+       status = "okay";
+};
+
+&mii_conv1 {
+       renesas,miic-input = <ETHSS_ETHSW_PORT1>;
+       status = "okay";
+};
+
+&mii_conv2 {
+       renesas,miic-input = <ETHSS_GMAC2_PORT>;
+       status = "okay";
+};
+
+&mii_conv3 {
+       renesas,miic-input = <ETHSS_GMAC1_PORT>;
+       status = "okay";
+};
+
 &ohci {
        dr_mode = "otg";
        status = "okay";