iommu/amd: Rearrange GCR3 table setup code

Consolidate GCR3 table related code in one place so that its easy
to maintain.

Note that this patch doesn't move __set_gcr3/__clear_gcr3. We are moving
GCR3 table from per domain to per device. Following series will rework
these functions. During that time I will move these functions as well.

No functional changes intended.

Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20240205115615.6053-9-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index dc8afcefd3ccb4f824e05a7d39ed5298102f4406..d8b42b0a253923295be4ffd2c0d9c95a889f217f 100644 (file)
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1714,6 +1714,38 @@ static int setup_gcr3_table(struct protection_domain *domain, int pasids)
        return 0;
 }
 
+static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
+{
+       int index;
+       u64 *pte;
+
+       while (true) {
+
+               index = (pasid >> (9 * level)) & 0x1ff;
+               pte   = &root[index];
+
+               if (level == 0)
+                       break;
+
+               if (!(*pte & GCR3_VALID)) {
+                       if (!alloc)
+                               return NULL;
+
+                       root = (void *)get_zeroed_page(GFP_ATOMIC);
+                       if (root == NULL)
+                               return NULL;
+
+                       *pte = iommu_virt_to_phys(root) | GCR3_VALID;
+               }
+
+               root = iommu_phys_to_virt(*pte & PAGE_MASK);
+
+               level -= 1;
+       }
+
+       return pte;
+}
+
 static void set_dte_entry(struct amd_iommu *iommu,
                          struct iommu_dev_data *dev_data)
 {
@@ -2737,38 +2769,6 @@ int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
        return ret;
 }
 
-static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
-{
-       int index;
-       u64 *pte;
-
-       while (true) {
-
-               index = (pasid >> (9 * level)) & 0x1ff;
-               pte   = &root[index];
-
-               if (level == 0)
-                       break;
-
-               if (!(*pte & GCR3_VALID)) {
-                       if (!alloc)
-                               return NULL;
-
-                       root = (void *)get_zeroed_page(GFP_ATOMIC);
-                       if (root == NULL)
-                               return NULL;
-
-                       *pte = iommu_virt_to_phys(root) | GCR3_VALID;
-               }
-
-               root = iommu_phys_to_virt(*pte & PAGE_MASK);
-
-               level -= 1;
-       }
-
-       return pte;
-}
-
 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
                      unsigned long cr3)
 {