]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL
authorImre Deak <imre.deak@intel.com>
Fri, 14 Feb 2025 14:19:52 +0000 (16:19 +0200)
committerImre Deak <imre.deak@intel.com>
Fri, 14 Feb 2025 19:39:05 +0000 (21:39 +0200)
Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
where this had an off-by-one error.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-3-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/i915_reg.h

index 69678220a8ca21878616e704e716ecaf47b9ab52..550e6ed6eaa1c338b7549cf16e3fe6a2c5e0beb2 100644 (file)
@@ -3507,7 +3507,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
                intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
                             XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
 
-               buf_ctl |= DDI_PORT_WIDTH(lane_count);
+               buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
                if (DISPLAY_VER(dev_priv) >= 20)
                        buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
index 670cd2371f9472c4627a8da3412c9dffdebeb8b2..3eea191f201753ac9f3b8add8f7e2b69eb351764 100644 (file)
@@ -3639,7 +3639,7 @@ enum skl_power_gate {
 #define  DDI_BUF_IS_IDLE                       (1 << 7)
 #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP          REG_BIT(6)
 #define  DDI_A_4_LANES                         (1 << 4)
-#define  DDI_PORT_WIDTH(width)                 (((width) - 1) << 1)
+#define  DDI_PORT_WIDTH(width)                 (((width) == 3 ? 4 : ((width) - 1)) << 1)
 #define  DDI_PORT_WIDTH_MASK                   (7 << 1)
 #define  DDI_PORT_WIDTH_SHIFT                  1
 #define  DDI_INIT_DISPLAY_DETECTED             (1 << 0)