RISC-V: Support Zce 1.0

Zce is the extension defined in code-size-reduction

Ref: https://github.com/riscvarchive/riscv-code-size-reduction

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index bbadf22d6946d4687e85df901d482302f704da28..93644423a3deae4a771d928ff522aea1d4e015bc 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1165,6 +1165,18 @@ check_implicit_for_i (riscv_parse_subset_t *rps ATTRIBUTE_UNUSED,
              && subset->minor_version < 1));
 }
 
+/* Add the IMPLICIT only when the 'f' extension is also available
+   and XLEN is 32.  */
+
+static bool
+check_implicit_for_zcf (riscv_parse_subset_t *rps,
+                       const riscv_subset_t *subset ATTRIBUTE_UNUSED)
+{
+  riscv_subset_t *tmp = NULL;
+  return *rps->xlen == 32
+        && riscv_lookup_subset (rps->subset_list, "f", &tmp);
+}
+
 /* Record all implicit information for the subsets.  */
 struct riscv_implicit_subset
 {
@@ -1216,6 +1228,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvl128b", "+zvl64b", check_implicit_always},
   {"zvl64b", "+zvl32b", check_implicit_always},
 
+  {"zce", "+zca,+zcb,+zcmp,+zcmt", check_implicit_always},
+  {"zce", "+zcf", check_implicit_for_zcf},
   {"zcb", "+zca", check_implicit_always},
   {"zcd", "+d,+zca", check_implicit_always},
   {"zcf", "+f,+zca", check_implicit_always},
@@ -1442,6 +1456,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"ztso",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zca",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcb",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zce",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcf",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcd",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zcmop",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },

diff --git a/gas/NEWS b/gas/NEWS
index 9d845a8bdca415609ee0b0085d09670804b566c2..42c3329d83ef7315bc4e0665e0da5eaf747b031e 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -12,7 +12,7 @@
 
 * Add support for RISC-V standard extensions:
   ssqosid v1.0, ssnpm v1.0, smnpm v1.0, smmpm v1.0, sspm v1.0, supm v1.0,
-  sha v1.0.
+  sha v1.0, zce v1.0.
 
 * Add support for RISC-V vendor extensions:
   T-Head: xtheadvdot v1.0.

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index bcc3a8f1fbd09eb010ea4b749c47cdcb1be138a3..87faa87ce45a7ef9345af429dfef5bc488b73042 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -102,6 +102,7 @@ All available -march extensions for RISC-V:
        ztso                                    1.0
        zca                                     1.0
        zcb                                     1.0
+       zce                                     1.0
        zcf                                     1.0
        zcd                                     1.0
        zcmop                                   1.0

diff --git a/gas/testsuite/gas/riscv/march-imply-zce-f-32.d b/gas/testsuite/gas/riscv/march-imply-zce-f-32.d
new file mode 100644 (file)
index 0000000..e0cca82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-zce-f-32.d
@@ -0,0 +1,6 @@
+#as: -march=rv32if_zce -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0"

diff --git a/gas/testsuite/gas/riscv/march-imply-zce-f-64.d b/gas/testsuite/gas/riscv/march-imply-zce-f-64.d
new file mode 100644 (file)
index 0000000..f0ccd7a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-zce-f-64.d
@@ -0,0 +1,6 @@
+#as: -march=rv64if_zce -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0"

diff --git a/gas/testsuite/gas/riscv/march-imply-zce.d b/gas/testsuite/gas/riscv/march-imply-zce.d
new file mode 100644 (file)
index 0000000..fd1cd3f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-zce.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zce -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0"