drm/amdgpu: Do not wait for MP0_C2PMSG_33 IFWI init in SRIOV

SRIOV does not need to wait for IFWI init, and MP0_C2PMSG_33 is blocked
for VF access.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Vignesh Chander <Vignesh.Chander@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index c71356cb393d1d756b6c2d5bec00d7c65bb691a8..0cb8aea93a704e68d4f52c0f6c32409f39312c25 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -260,19 +260,21 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
        u32 msg;
        int i, ret = 0;
 
-       /* It can take up to a second for IFWI init to complete on some dGPUs,
-        * but generally it should be in the 60-100ms range.  Normally this starts
-        * as soon as the device gets power so by the time the OS loads this has long
-        * completed.  However, when a card is hotplugged via e.g., USB4, we need to
-        * wait for this to complete.  Once the C2PMSG is updated, we can
-        * continue.
-        */
+       if (!amdgpu_sriov_vf(adev)) {
+               /* It can take up to a second for IFWI init to complete on some dGPUs,
+                * but generally it should be in the 60-100ms range.  Normally this starts
+                * as soon as the device gets power so by the time the OS loads this has long
+                * completed.  However, when a card is hotplugged via e.g., USB4, we need to
+                * wait for this to complete.  Once the C2PMSG is updated, we can
+                * continue.
+                */
 
-       for (i = 0; i < 1000; i++) {
-               msg = RREG32(mmMP0_SMN_C2PMSG_33);
-               if (msg & 0x80000000)
-                       break;
-               usleep_range(1000, 1100);
+               for (i = 0; i < 1000; i++) {
+                       msg = RREG32(mmMP0_SMN_C2PMSG_33);
+                       if (msg & 0x80000000)
+                               break;
+                       usleep_range(1000, 1100);
+               }
        }
 
        vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;