]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm: renesas: rz-du: Add RZ/G2UL DU Support
authorBiju Das <biju.das.jz@bp.renesas.com>
Thu, 22 Aug 2024 16:23:15 +0000 (17:23 +0100)
committerTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Mon, 26 Aug 2024 09:47:04 +0000 (12:47 +0300)
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI interface and supports a maximum resolution of WXGA along
with 2 RPFs to support the blending of two picture layers and raster
operations (ROPs).

The DU module is connected to VSPD. Add RZ/G2UL DU support.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240822162320.5084-3-biju.das.jz@bp.renesas.com
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c

index 6e7aac6219bed32dc2a161e6b50478ef07be793c..c4c1474d487e72df23e5a77340d226cc0e934f40 100644 (file)
@@ -28,6 +28,7 @@
 #include "rzg2l_du_vsp.h"
 
 #define DU_MCR0                        0x00
+#define DU_MCR0_DPI_OE         BIT(0)
 #define DU_MCR0_DI_EN          BIT(8)
 
 #define DU_DITR0               0x10
@@ -216,9 +217,14 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc)
 
 static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start)
 {
+       struct rzg2l_du_crtc_state *rstate = to_rzg2l_crtc_state(rcrtc->crtc.state);
        struct rzg2l_du_device *rcdu = rcrtc->dev;
+       u32 val = DU_MCR0_DI_EN;
 
-       writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
+       if (rstate->outputs & BIT(RZG2L_DU_OUTPUT_DPAD0))
+               val |= DU_MCR0_DPI_OE;
+
+       writel(start ? val : 0, rcdu->mmio + DU_MCR0);
 }
 
 static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)
index e5eca8691a331ccdec9a3be2ca0560d798bfbe36..bc7c381f92ac31f1307fc629481602b3cb55cbf2 100644 (file)
  * Device Information
  */
 
+static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
+       .channels_mask = BIT(0),
+       .routes = {
+               [RZG2L_DU_OUTPUT_DPAD0] = {
+                       .possible_outputs = BIT(0),
+                       .port = 0,
+               },
+       },
+};
+
 static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
        .channels_mask = BIT(0),
        .routes = {
@@ -40,6 +50,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
 };
 
 static const struct of_device_id rzg2l_du_of_table[] = {
+       { .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
        { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
        { /* sentinel */ }
 };
index 07b312b6f81ea1286c5c26a1d419938d74f50678..b99217b4e05d7df9a3fe54db365fcbeca0e7e831 100644 (file)
@@ -183,7 +183,8 @@ static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu)
 
                /* Find the output route corresponding to the port number. */
                for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {
-                       if (rcdu->info->routes[i].port == ep.port) {
+                       if (rcdu->info->routes[i].possible_outputs &&
+                           rcdu->info->routes[i].port == ep.port) {
                                output = i;
                                break;
                        }