]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
cpufreq: ACPI: Simplify MSR read on the boot CPU
authorChang S. Bae <chang.seok.bae@intel.com>
Wed, 6 Nov 2024 18:23:13 +0000 (10:23 -0800)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Tue, 12 Nov 2024 20:42:29 +0000 (21:42 +0100)
Replace the 32-bit MSR access function with a 64-bit variant to simplify
the call site, eliminating unnecessary 32-bit value manipulations.

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Link: https://patch.msgid.link/20241106182313.165297-1-chang.seok.bae@intel.com
[ rjw: Subject edit ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
drivers/cpufreq/acpi-cpufreq.c

index 433eb597c2b80fbcb2a2cb105e8521a07d504665..c9ebacf5c88e2448cbe952da1946d4ec941a5b1c 100644 (file)
@@ -73,20 +73,17 @@ static unsigned int acpi_pstate_strict;
 
 static bool boost_state(unsigned int cpu)
 {
-       u32 lo, hi;
        u64 msr;
 
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_INTEL:
        case X86_VENDOR_CENTAUR:
        case X86_VENDOR_ZHAOXIN:
-               rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
-               msr = lo | ((u64)hi << 32);
+               rdmsrl_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr);
                return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
        case X86_VENDOR_HYGON:
        case X86_VENDOR_AMD:
-               rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
-               msr = lo | ((u64)hi << 32);
+               rdmsrl_on_cpu(cpu, MSR_K7_HWCR, &msr);
                return !(msr & MSR_K7_HWCR_CPB_DIS);
        }
        return false;