i386: Generate strict_low_part QImode insn with high input register

Following testcase:

struct S1
{
  unsigned char val;
  unsigned char pad1;
  unsigned short pad2;
};

struct S2
{
  unsigned char pad1;
  unsigned char val;
  unsigned short pad2;
};

struct S1 test_and (struct S1 a, struct S2 b)
{
  a.val &= b.val;

  return a;
}

compiles with -O2 to:

	movl    %esi, %edx
	movl    %edi, %eax
	movzbl  %dh, %esi
	andb    %sil, %al

ANDB could use high register %dh instead of %sil:

	movl    %edi, %eax
	movl    %esi, %edx
	andb    %dh, %al

Patch introduces strict_low_part QImode insn patterns with one of
its input arguments extracted from high register.

	PR target/78904

gcc/ChangeLog:

	* config/i386/i386.md (*addqi_ext<mode>_1_slp):
	New define_insn_and_split pattern.
	(*subqi_ext<mode>_1_slp): Ditto.
	(*<any_logic:code>qi_ext<mode>_1_slp): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr78904-7.c: New test.
	* gcc.target/i386/pr78904-7a.c: New test.
	* gcc.target/i386/pr78904-7b.c: New test.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 84cc50c7bb214bd53352495e361e95c3e14c1cce..6136e46b1bcf1195b3e90809a98c2ad4c9988f8a 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6615,6 +6615,36 @@
        (const_string "alu")))
    (set_attr "mode" "<MODE>")])
 
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*addqi_ext<mode>_1_slp"
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+Q,&Q"))
+       (plus:QI
+         (subreg:QI
+           (match_operator:SWI248 3 "extract_operator"
+             [(match_operand 2 "int248_register_operand" "Q,Q")
+              (const_int 8)
+              (const_int 8)]) 0)
+         (match_operand:QI 1 "nonimmediate_operand" "0,!Q")))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "@
+   add{b}\t{%h2, %0|%0, %h2}
+   #"
+  "reload_completed
+   && !rtx_equal_p (operands[0], operands[1])"
+  [(set (strict_low_part (match_dup 0)) (match_dup 1))
+   (parallel
+     [(set (strict_low_part (match_dup 0))
+          (plus:QI
+            (subreg:QI
+              (match_op_dup 3
+                [(match_dup 0) (const_int 8) (const_int 8)]) 0)
+          (match_dup 1)))
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
 ;; Split non destructive adds if we cannot use lea.
 (define_split
   [(set (match_operand:SWI48 0 "register_operand")
@@ -7628,6 +7658,36 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*subqi_ext<mode>_1_slp"
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+Q,&Q"))
+       (minus:QI
+         (match_operand:QI 1 "nonimmediate_operand" "0,!Q")
+         (subreg:QI
+           (match_operator:SWI248 3 "extract_operator"
+             [(match_operand 2 "int248_register_operand" "Q,Q")
+              (const_int 8)
+              (const_int 8)]) 0)))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "@
+   sub{b}\t{%h2, %0|%0, %h2}
+   #"
+  "reload_completed
+   && !rtx_equal_p (operands[0], operands[1])"
+  [(set (strict_low_part (match_dup 0)) (match_dup 1))
+   (parallel
+     [(set (strict_low_part (match_dup 0))
+          (minus:QI
+          (match_dup 1)
+            (subreg:QI
+              (match_op_dup 3
+                [(match_dup 0) (const_int 8) (const_int 8)]) 0)))
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
 (define_insn "*sub<mode>_2"
   [(set (reg FLAGS_REG)
        (compare
@@ -11423,6 +11483,36 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "<MODE>")])
 
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*<code>qi_ext<mode>_1_slp"
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+Q,&Q"))
+       (any_logic:QI
+         (subreg:QI
+           (match_operator:SWI248 3 "extract_operator"
+             [(match_operand 2 "int248_register_operand" "Q,Q")
+              (const_int 8)
+              (const_int 8)]) 0)
+         (match_operand:QI 1 "nonimmediate_operand" "0,!Q")))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "@
+   <logic>{b}\t{%h2, %0|%0, %h2}
+   #"
+  "reload_completed
+   && !rtx_equal_p (operands[0], operands[1])"
+  [(set (strict_low_part (match_dup 0)) (match_dup 1))
+   (parallel
+     [(set (strict_low_part (match_dup 0))
+          (any_logic:QI
+          (match_dup 1)
+            (subreg:QI
+              (match_op_dup 3
+                [(match_dup 0) (const_int 8) (const_int 8)]) 0)))
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
 (define_split
   [(set (match_operand:SWI248 0 "register_operand")
        (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")

diff --git a/gcc/testsuite/gcc.target/i386/pr78904-7.c b/gcc/testsuite/gcc.target/i386/pr78904-7.c
new file mode 100644 (file)
index 0000000..e52a269
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-7.c
@@ -0,0 +1,64 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+/* { dg-final { scan-assembler-not "movb" } } */
+
+struct S1
+{
+  unsigned char val;
+  unsigned char pad1;
+  unsigned short pad2;
+};
+
+struct S2
+{
+  unsigned char pad1;
+  unsigned char val;
+  unsigned short pad2;
+};
+
+struct S1 test_and (struct S1 a, struct S2 b)
+{
+  a.val &= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb" } } */
+
+struct S1 test_or (struct S1 a, struct S2 b)
+{
+  a.val |= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb" } } */
+
+struct S1 test_xor (struct S1 a, struct S2 b)
+{
+  a.val ^= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
+
+struct S1 test_add (struct S1 a, struct S2 b)
+{
+  a.val += b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb" } } */
+
+struct S1 test_sub (struct S1 a, struct S2 b)
+{
+  a.val -= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]subb" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr78904-7a.c b/gcc/testsuite/gcc.target/i386/pr78904-7a.c
new file mode 100644 (file)
index 0000000..c060a48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-7a.c
@@ -0,0 +1,62 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+/* { dg-final { scan-assembler-not "movb" } } */
+
+struct S1
+{
+  unsigned char val;
+  unsigned char pad1;
+};
+
+struct S2
+{
+  unsigned char pad1;
+  unsigned char val;
+};
+
+struct S1 test_and (struct S1 a, struct S2 b)
+{
+  a.val &= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb" } } */
+
+struct S1 test_or (struct S1 a, struct S2 b)
+{
+  a.val |= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb" } } */
+
+struct S1 test_xor (struct S1 a, struct S2 b)
+{
+  a.val ^= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
+
+struct S1 test_add (struct S1 a, struct S2 b)
+{
+  a.val += b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb" } } */
+
+struct S1 test_sub (struct S1 a, struct S2 b)
+{
+  a.val -= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]subb" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr78904-7b.c b/gcc/testsuite/gcc.target/i386/pr78904-7b.c
new file mode 100644 (file)
index 0000000..76dc048
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-7b.c
@@ -0,0 +1,66 @@
+/* PR target/78904 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+/* { dg-final { scan-assembler-not "movb" } } */
+
+struct S1
+{
+  unsigned char val;
+  unsigned char pad1;
+  unsigned short pad2;
+  unsigned int pad3;
+};
+
+struct S2
+{
+  unsigned char pad1;
+  unsigned char val;
+  unsigned short pad2;
+  unsigned int pad3;
+};
+
+struct S1 test_and (struct S1 a, struct S2 b)
+{
+  a.val &= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb" } } */
+
+struct S1 test_or (struct S1 a, struct S2 b)
+{
+  a.val |= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb" } } */
+
+struct S1 test_xor (struct S1 a, struct S2 b)
+{
+  a.val ^= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
+
+struct S1 test_add (struct S1 a, struct S2 b)
+{
+  a.val += b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb" } } */
+
+struct S1 test_sub (struct S1 a, struct S2 b)
+{
+  a.val -= b.val;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]subb" } } */