--- /dev/null
+From 33f1722eb86e45320a3dd7b3d42f6593a1d595c2 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <j4g8y7@gmail.com>
+Date: Mon, 21 Oct 2024 19:32:48 +0200
+Subject: clk: qcom: clk-alpha-pll: fix alpha mode configuration
+
+From: Gabor Juhos <j4g8y7@gmail.com>
+
+commit 33f1722eb86e45320a3dd7b3d42f6593a1d595c2 upstream.
+
+Commit c45ae598fc16 ("clk: qcom: support for alpha mode configuration")
+added support for configuring alpha mode, but it seems that the feature
+was never working in practice.
+
+The value of the alpha_{en,mode}_mask members of the configuration gets
+added to the value parameter passed to the regmap_update_bits() function,
+however the same values are not getting applied to the bitmask. As the
+result, the respective bits in the USER_CTL register are never modifed
+which leads to improper configuration of several PLLs.
+
+The following table shows the PLL configurations where the 'alpha_en_mask'
+member is set and which are passed as a parameter for the
+clk_alpha_pll_configure() function. In the table the 'expected rate' column
+shows the rate the PLL should run at with the given configuration, and
+the 'real rate' column shows the rate the PLL runs at actually. The real
+rates has been verified on hardwareOn IPQ* platforms, on other platforms,
+those are computed values only.
+
+ file pll expected rate real rate
+ dispcc-qcm2290.c disp_cc_pll0 768.0 MHz 768.0 MHz
+ dispcc-sm6115.c disp_cc_pll0 768.0 MHz 768.0 MHz
+ gcc-ipq5018.c ubi32_pll 1000.0 MHz != 984.0 MHz
+ gcc-ipq6018.c nss_crypto_pll 1200.0 MHz 1200.0 MHz
+ gcc-ipq6018.c ubi32_pll 1497.6 MHz != 1488.0 MHz
+ gcc-ipq8074.c nss_crypto_pll 1200.0 MHz != 1190.4 MHz
+ gcc-qcm2290.c gpll11 532.0 MHz != 518.4 MHz
+ gcc-qcm2290.c gpll8 533.2 MHz != 518.4 MHz
+ gcc-qcs404.c gpll3 921.6 MHz 921.6 MHz
+ gcc-sm6115.c gpll11 600.0 MHz != 595.2 MHz
+ gcc-sm6115.c gpll8 800.0 MHz != 787.2 MHz
+ gpucc-sdm660.c gpu_cc_pll0 800.0 MHz != 787.2 MHz
+ gpucc-sdm660.c gpu_cc_pll1 740.0 MHz != 729.6 MHz
+ gpucc-sm6115.c gpu_cc_pll0 1200.0 MHz != 1190.4 MHz
+ gpucc-sm6115.c gpu_cc_pll1 640.0 MHz != 633.6 MHz
+ gpucc-sm6125.c gpu_pll0 1020.0 MHz != 1017.6 MHz
+ gpucc-sm6125.c gpu_pll1 930.0 MHz != 921.6 MHz
+ mmcc-sdm660.c mmpll8 930.0 MHz != 921.6 MHz
+ mmcc-sdm660.c mmpll5 825.0 MHz != 806.4 MHz
+
+As it can be seen from the above, there are several PLLs which are
+configured incorrectly.
+
+Change the code to apply both 'alpha_en_mask' and 'alpha_mode_mask'
+values to the bitmask in order to configure the alpha mode correctly.
+
+Applying the 'alpha_en_mask' fixes the initial rate of the PLLs showed
+in the table above. Since the 'alpha_mode_mask' is not used by any driver
+currently, that part of the change causes no functional changes.
+
+Cc: stable@vger.kernel.org
+Fixes: c45ae598fc16 ("clk: qcom: support for alpha mode configuration")
+Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Tested-by: Gabor Juhos <j4g8y7@gmail.com>
+Link: https://lore.kernel.org/r/20241021-fix-alpha-mode-config-v1-1-f32c254e02bc@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/qcom/clk-alpha-pll.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/qcom/clk-alpha-pll.c
++++ b/drivers/clk/qcom/clk-alpha-pll.c
+@@ -240,6 +240,8 @@ void clk_alpha_pll_configure(struct clk_
+ mask |= config->pre_div_mask;
+ mask |= config->post_div_mask;
+ mask |= config->vco_mask;
++ mask |= config->alpha_en_mask;
++ mask |= config->alpha_mode_mask;
+
+ regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
+
--- /dev/null
+From 89aa5925d201b90a48416784831916ca203658f9 Mon Sep 17 00:00:00 2001
+From: Anastasia Belova <abelova@astralinux.ru>
+Date: Tue, 3 Dec 2024 11:42:31 +0300
+Subject: clk: qcom: clk-rpmh: prevent integer overflow in recalc_rate
+
+From: Anastasia Belova <abelova@astralinux.ru>
+
+commit 89aa5925d201b90a48416784831916ca203658f9 upstream.
+
+aggr_state and unit fields are u32. The result of their
+multiplication may not fit in this type.
+
+Add explicit casting to prevent overflow.
+
+Found by Linux Verification Center (linuxtesting.org) with SVACE.
+
+Fixes: 04053f4d23a4 ("clk: qcom: clk-rpmh: Add IPA clock support")
+Cc: stable@vger.kernel.org # 5.4+
+Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
+Link: https://lore.kernel.org/r/20241203084231.6001-1-abelova@astralinux.ru
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/qcom/clk-rpmh.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/clk-rpmh.c
++++ b/drivers/clk/qcom/clk-rpmh.c
+@@ -331,7 +331,7 @@ static unsigned long clk_rpmh_bcm_recalc
+ {
+ struct clk_rpmh *c = to_clk_rpmh(hw);
+
+- return c->aggr_state * c->unit;
++ return (unsigned long)c->aggr_state * c->unit;
+ }
+
+ static const struct clk_ops clk_rpmh_bcm_ops = {
--- /dev/null
+From 16414720045de30945b8d14b7907e0cbf81a4b49 Mon Sep 17 00:00:00 2001
+From: Cody Eksal <masterr3c0rd@epochal.quest>
+Date: Fri, 8 Nov 2024 20:37:37 -0400
+Subject: clk: sunxi-ng: a100: enable MMC clock reparenting
+
+From: Cody Eksal <masterr3c0rd@epochal.quest>
+
+commit 16414720045de30945b8d14b7907e0cbf81a4b49 upstream.
+
+While testing the MMC nodes proposed in [1], it was noted that mmc0/1
+would fail to initialize, with "mmc: fatal err update clk timeout" in
+the kernel logs. A closer look at the clock definitions showed that the MMC
+MPs had the "CLK_SET_RATE_NO_REPARENT" flag set. No reason was given for
+adding this flag in the first place, and its original purpose is unknown,
+but it doesn't seem to make sense and results in severe limitations to MMC
+speeds. Thus, remove this flag from the 3 MMC MPs.
+
+[1] https://msgid.link/20241024170540.2721307-10-masterr3c0rd@epochal.quest
+
+Fixes: fb038ce4db55 ("clk: sunxi-ng: add support for the Allwinner A100 CCU")
+Cc: stable@vger.kernel.org
+Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Link: https://patch.msgid.link/20241109003739.3440904-1-masterr3c0rd@epochal.quest
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
+@@ -437,7 +437,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+- CLK_SET_RATE_NO_REPARENT);
++ 0);
+
+ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
+ 0, 4, /* M */
+@@ -445,7 +445,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+- CLK_SET_RATE_NO_REPARENT);
++ 0);
+
+ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
+ 0, 4, /* M */
+@@ -453,7 +453,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+- CLK_SET_RATE_NO_REPARENT);
++ 0);
+
+ static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
+ static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
drm-komeda-add-check-for-komeda_get_layer_fourcc_list.patch
bluetooth-l2cap-handle-null-sock-pointer-in-l2cap_sock_alloc.patch
bluetooth-l2cap-accept-zero-as-a-special-value-for-mtu-auto-selection.patch
+clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch
+clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch
+clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
