--- /dev/null
+From dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 14 May 2021 11:26:37 +0100
+Subject: ARM: 9081/1: fix gcc-10 thumb2-kernel regression
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+commit dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 upstream.
+
+When building the kernel wtih gcc-10 or higher using the
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly
+different set of registers for the inline assembly in cpu_init() that
+subsequently results in a corrupt kernel stack as well as remaining in
+FIQ mode. If a banked register is used for the last argument, the wrong
+version of that register gets loaded into CPSR_c. When building in Arm
+mode, the arguments are passed as immediate values and the bug cannot
+happen.
+
+This got introduced when Daniel reworked the FIQ handling and was
+technically always broken, but happened to work with both clang and gcc
+before gcc-10 as long as they picked one of the lower registers.
+This is probably an indication that still very few people build the
+kernel in Thumb2 mode.
+
+Marek pointed out the problem on IRC, Arnd narrowed it down to this
+inline assembly and Russell pinpointed the exact bug.
+
+Change the constraints to force the final mode switch to use a non-banked
+register for the argument to ensure that the correct constant gets loaded.
+Another alternative would be to always use registers for the constant
+arguments to avoid the #ifdef that has now become more complex.
+
+Cc: <stable@vger.kernel.org> # v3.18+
+Cc: Daniel Thompson <daniel.thompson@linaro.org>
+Reported-by: Marek Vasut <marek.vasut@gmail.com>
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm/kernel/setup.c | 16 +++++++++-------
+ 1 file changed, 9 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/kernel/setup.c
++++ b/arch/arm/kernel/setup.c
+@@ -547,9 +547,11 @@ void notrace cpu_init(void)
+ * In Thumb-2, msr with an immediate value is not allowed.
+ */
+ #ifdef CONFIG_THUMB2_KERNEL
+-#define PLC "r"
++#define PLC_l "l"
++#define PLC_r "r"
+ #else
+-#define PLC "I"
++#define PLC_l "I"
++#define PLC_r "I"
+ #endif
+
+ /*
+@@ -571,15 +573,15 @@ void notrace cpu_init(void)
+ "msr cpsr_c, %9"
+ :
+ : "r" (stk),
+- PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+ "I" (offsetof(struct stack, irq[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+ "I" (offsetof(struct stack, abt[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+ "I" (offsetof(struct stack, und[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
+ "I" (offsetof(struct stack, fiq[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
++ PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
+ : "r14");
+ #endif
+ }