net: phy: mediatek-ge-soc: Fix coding style

This patch fixes spelling errors, re-arrange vars with
reverse Xmas tree and remove unnecessary parens in
mediatek-ge-soc.c.

Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>

diff --git a/drivers/net/phy/mediatek-ge-soc.c b/drivers/net/phy/mediatek-ge-soc.c
index f4f9412d0cd7e256f4b2e962dd18974e1120c0fb..e9c422f4e24b0d2622f4a6c2d31a46d2572c8bbb 100644 (file)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
 
 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
 {
-       int i;
-       int bias[16] = {};
-       const int vals_9461[16] = { 7, 1, 4, 7,
-                                   7, 1, 4, 7,
-                                   7, 1, 4, 7,
-                                   7, 1, 4, 7 };
        const int vals_9481[16] = { 10, 6, 6, 10,
                                    10, 6, 6, 10,
                                    10, 6, 6, 10,
                                    10, 6, 6, 10 };
+       const int vals_9461[16] = { 7, 1, 4, 7,
+                                   7, 1, 4, 7,
+                                   7, 1, 4, 7,
+                                   7, 1, 4, 7 };
+       int bias[16] = {};
+       int i;
+
        switch (phydev->drv->phy_id) {
        case MTK_GPHY_ID_MT7981:
                /* We add some calibration to efuse values
@@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
 
 static int mt798x_phy_calibration(struct phy_device *phydev)
 {
+       struct nvmem_cell *cell;
        int ret = 0;
-       u32 *buf;
        size_t len;
-       struct nvmem_cell *cell;
+       u32 *buf;
 
        cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
        if (IS_ERR(cell)) {
@@ -1210,14 +1211,15 @@ static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
        return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
 }
 
-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-                                                BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
-                                                BIT(TRIGGER_NETDEV_LINK)        |
-                                                BIT(TRIGGER_NETDEV_LINK_10)     |
-                                                BIT(TRIGGER_NETDEV_LINK_100)    |
-                                                BIT(TRIGGER_NETDEV_LINK_1000)   |
-                                                BIT(TRIGGER_NETDEV_RX)          |
-                                                BIT(TRIGGER_NETDEV_TX));
+static const unsigned long supported_triggers =
+       BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+       BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
+       BIT(TRIGGER_NETDEV_LINK)        |
+       BIT(TRIGGER_NETDEV_LINK_10)     |
+       BIT(TRIGGER_NETDEV_LINK_100)    |
+       BIT(TRIGGER_NETDEV_LINK_1000)   |
+       BIT(TRIGGER_NETDEV_RX)          |
+       BIT(TRIGGER_NETDEV_TX);
 
 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
                                          unsigned long rules)
@@ -1415,7 +1417,7 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
         * LED_C and LED_D respectively. At the same time those pins are used to
         * bootstrap configuration of the reference clock source (LED_A),
         * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
-        * In practise this is done using a LED and a resistor pulling the pin
+        * In practice this is done using a LED and a resistor pulling the pin
         * either to GND or to VIO.
         * The detected value at boot time is accessible at run-time using the
         * TPBANK0 register located in the gpio base of the pinctrl, in order