drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs

Some SoCs such as SC7280 (used in the Fairphone 5) have only a single
DSC "hard slice" encoder.  The current hardcoded use of 2:2:1 topology
(2 LM and 2 DSC for a single interface) make it impossible to use
Display Stream Compression panels with mainline, which is exactly what's
installed on the Fairphone 5.

By loosening the hardcoded `num_dsc = 2` to fall back to `num_dsc =
1` when the catalog only contains one entry, we can trivially support
this phone and unblock further panel enablement on mainline.  A few
more supporting changes in this patch ensure hardcoded constants of 2
DSC encoders are replaced to count or read back the actual number of
DSC hardware blocks that are enabled for the given virtual encoder.
Likewise DSC_MODE_SPLIT_PANEL can no longer be unconditionally enabled.

Cc: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Tested-by: Danila Tikhonov <danila@jiaxyga.com>
Patchwork: https://patchwork.freedesktop.org/patch/633318/
Link: https://lore.kernel.org/r/20250122-dpu-111-topology-v2-1-505e95964af9@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 503dfd79b8f2d1c18c33535d25e939813c620e63..e3cbd65d2b13b1776a557176ce732c4f96ae76e3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -622,9 +622,9 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
                if (dpu_enc->phys_encs[i])
                        intf_count++;
 
-       /* See dpu_encoder_get_topology, we only support 2:2:1 topology */
-       if (dpu_enc->dsc)
-               num_dsc = 2;
+       for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
+               if (dpu_enc->hw_dsc[i])
+                       num_dsc++;
 
        return (num_dsc > 0) && (num_dsc > intf_count);
 }
@@ -686,13 +686,19 @@ static struct msm_display_topology dpu_encoder_get_topology(
 
        if (dsc) {
                /*
-                * In case of Display Stream Compression (DSC), we would use
-                * 2 DSC encoders, 2 layer mixers and 1 interface
-                * this is power optimal and can drive up to (including) 4k
-                * screens
+                * Use 2 DSC encoders and 2 layer mixers per single interface
+                * when Display Stream Compression (DSC) is enabled,
+                * and when enough DSC blocks are available.
+                * This is power-optimal and can drive up to (including) 4k
+                * screens.
                 */
-               topology.num_dsc = 2;
-               topology.num_lm = 2;
+               if (dpu_kms->catalog->dsc_count >= 2) {
+                       topology.num_dsc = 2;
+                       topology.num_lm = 2;
+               } else {
+                       topology.num_dsc = 1;
+                       topology.num_lm = 1;
+               }
                topology.num_intf = 1;
        }
 
@@ -2020,7 +2026,6 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
                                 struct drm_dsc_config *dsc)
 {
-       /* coding only for 2LM, 2enc, 1 dsc config */
        struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
        struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
        struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
@@ -2030,22 +2035,24 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
        int dsc_common_mode;
        int pic_width;
        u32 initial_lines;
+       int num_dsc = 0;
        int i;
 
        for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
                hw_pp[i] = dpu_enc->hw_pp[i];
                hw_dsc[i] = dpu_enc->hw_dsc[i];
 
-               if (!hw_pp[i] || !hw_dsc[i]) {
-                       DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
-                       return;
-               }
+               if (!hw_pp[i] || !hw_dsc[i])
+                       break;
+
+               num_dsc++;
        }
 
-       dsc_common_mode = 0;
        pic_width = dsc->pic_width;
 
-       dsc_common_mode = DSC_MODE_SPLIT_PANEL;
+       dsc_common_mode = 0;
+       if (num_dsc > 1)
+               dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
        if (dpu_encoder_use_dsc_merge(enc_master->parent))
                dsc_common_mode |= DSC_MODE_MULTIPLEX;
        if (enc_master->intf_mode == INTF_MODE_VIDEO)
@@ -2054,14 +2061,10 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
        this_frame_slices = pic_width / dsc->slice_width;
        intf_ip_w = this_frame_slices * dsc->slice_width;
 
-       /*
-        * dsc merge case: when using 2 encoders for the same stream,
-        * no. of slices need to be same on both the encoders.
-        */
-       enc_ip_w = intf_ip_w / 2;
+       enc_ip_w = intf_ip_w / num_dsc;
        initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
 
-       for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
+       for (i = 0; i < num_dsc; i++)
                dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
                                         dsc, dsc_common_mode, initial_lines);
 }