rs6000, extend the current vec_{un,}signed{e,o} built-ins

The built-ins __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds
convert a vector of floats to a vector of signed/unsigned long long ints.
Extend the existing vec_{un,}signed{e,o} built-ins to handle the argument
vector of floats to return a vector of even/odd signed/unsigned integers.

The define expands vsignede_v4sf, vsignedo_v4sf, vunsignede_v4sf,
vunsignedo_v4sf are added to support the new vec_{un,}signed{e,o}
built-ins.

The built-ins __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds are
now for internal use only. They are not documented and they do not
have test cases.

Add testcases and update documentation.

gcc/ChangeLog:
	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvspsxds,
	__builtin_vsx_xvcvspuxds): Rename to __builtin_vsignede_v4sf,
	__builtin_vunsignede_v4sf respectively.
	(XVCVSPSXDS, XVCVSPUXDS): Rename to VEC_VSIGNEDE_V4SF,
	VEC_VUNSIGNEDE_V4SF respectively.
	(__builtin_vsignedo_v4sf, __builtin_vunsignedo_v4sf): New
	built-in definitions.
	* config/rs6000/rs6000-overload.def (vec_signede, vec_signedo,
	vec_unsignede, vec_unsignedo): Add new overloaded specifications.
	* config/rs6000/vsx.md (vsignede_v4sf, vsignedo_v4sf,
	vunsignede_v4sf, vunsignedo_v4sf): New define_expands.
	* doc/extend.texi (vec_signedo, vec_signede, vec_unsignedo,
	vec_unsignede): Add documentation for new overloaded built-ins to
	convert vector float to vector {un,}signed long long.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/builtins-3-runnable.c
	(test_unsigned_int_result, test_ll_unsigned_int_result): Add
	new argument.
	(vec_signede, vec_signedo, vec_unsignede, vec_unsignedo): New
	tests for the overloaded built-ins.

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index f0aee29f1a1dd04447aa9246b991993c7ff4633c..5f353f5faeb28e857202c2f121eba3d540b38228 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1697,11 +1697,17 @@
   const vd __builtin_vsx_xvcvspdp (vf);
     XVCVSPDP vsx_xvcvspdp {}
 
-  const vsll __builtin_vsx_xvcvspsxds (vf);
-    XVCVSPSXDS vsx_xvcvspsxds {}
+  const vsll __builtin_vsignede_v4sf (vf);
+    VEC_VSIGNEDE_V4SF vsignede_v4sf {}
 
-  const vsll __builtin_vsx_xvcvspuxds (vf);
-    XVCVSPUXDS vsx_xvcvspuxds {}
+  const vsll __builtin_vsignedo_v4sf (vf);
+    VEC_VSIGNEDO_V4SF vsignedo_v4sf {}
+
+  const vull __builtin_vunsignede_v4sf (vf);
+    VEC_VUNSIGNEDE_V4SF vunsignede_v4sf {}
+
+  const vull __builtin_vunsignedo_v4sf (vf);
+    VEC_VUNSIGNEDO_V4SF vunsignedo_v4sf {}
 
   const vd __builtin_vsx_xvcvsxddp (vsll);
     XVCVSXDDP vsx_floatv2div2df2 {}

diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 84bd9ae6554a48663eab7e57a17b44a2dfc31b6c..4d857bb1af3e40f6a6391739effc07c25ee8f4c2 100644 (file)
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -3307,10 +3307,14 @@
 [VEC_SIGNEDE, vec_signede, __builtin_vec_vsignede]
   vsi __builtin_vec_vsignede (vd);
     VEC_VSIGNEDE_V2DF
+  vsll __builtin_vec_vsignede (vf);
+    VEC_VSIGNEDE_V4SF
 
 [VEC_SIGNEDO, vec_signedo, __builtin_vec_vsignedo]
   vsi __builtin_vec_vsignedo (vd);
     VEC_VSIGNEDO_V2DF
+  vsll __builtin_vec_vsignedo (vf);
+    VEC_VSIGNEDO_V4SF
 
 [VEC_SIGNEXTI, vec_signexti, __builtin_vec_signexti]
   vsi __builtin_vec_signexti (vsc);
@@ -4433,10 +4437,14 @@
 [VEC_UNSIGNEDE, vec_unsignede, __builtin_vec_vunsignede]
   vui __builtin_vec_vunsignede (vd);
     VEC_VUNSIGNEDE_V2DF
+  vull __builtin_vec_vunsignede (vf);
+    VEC_VUNSIGNEDE_V4SF
 
 [VEC_UNSIGNEDO, vec_unsignedo, __builtin_vec_vunsignedo]
   vui __builtin_vec_vunsignedo (vd);
     VEC_VUNSIGNEDO_V2DF
+  vull __builtin_vec_vunsignedo (vf);
+    VEC_VUNSIGNEDO_V4SF
 
 [VEC_VEE, vec_extract_exp, __builtin_vec_extract_exp]
   vui __builtin_vec_extract_exp (vf);

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 23ce5c7405102640d4dc9d48cf473f0348dee5dc..8001d1778b895c9df6b38ab560691091a116eef4 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2704,6 +2704,90 @@
   DONE;
 })
 
+;; Convert float vector even elements to signed long long vector
+(define_expand "vsignede_v4sf"
+  [(match_operand:V2DI 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvspsxds_be (operands[0], operands[1]));
+  else
+    {
+      /* Shift left one word to put even word in correct location.  */
+      rtx rtx_tmp = gen_reg_rtx (V4SFmode);
+      rtx rtx_val = GEN_INT (4);
+      emit_insn (gen_altivec_vsldoi_v4sf (rtx_tmp, operands[1], operands[1],
+                                         rtx_val));
+      emit_insn (gen_vsx_xvcvspsxds_le (operands[0], rtx_tmp));
+    }
+
+  DONE;
+})
+
+;; Convert float vector odd elements to signed long long vector
+(define_expand "vsignedo_v4sf"
+  [(match_operand:V2DI 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    {
+      /* Shift left one word to put even word in correct location.  */
+      rtx rtx_tmp = gen_reg_rtx (V4SFmode);
+      rtx rtx_val = GEN_INT (4);
+      emit_insn (gen_altivec_vsldoi_v4sf (rtx_tmp, operands[1], operands[1],
+                                         rtx_val));
+      emit_insn (gen_vsx_xvcvspsxds_be (operands[0], rtx_tmp));
+    }
+  else
+    emit_insn (gen_vsx_xvcvspsxds_le (operands[0], operands[1]));
+
+  DONE;
+})
+
+;; Convert float vector of even vector elements to unsigned long long vector
+(define_expand "vunsignede_v4sf"
+  [(match_operand:V2DI 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvspuxds_be (operands[0], operands[1]));
+  else
+    {
+      /* Shift left one word to put even word in correct location.  */
+      rtx rtx_tmp = gen_reg_rtx (V4SFmode);
+      rtx rtx_val = GEN_INT (4);
+      emit_insn (gen_altivec_vsldoi_v4sf (rtx_tmp, operands[1], operands[1],
+                                         rtx_val));
+      emit_insn (gen_vsx_xvcvspuxds_le (operands[0], rtx_tmp));
+    }
+
+  DONE;
+})
+
+;; Convert float vector of odd elements to unsigned long long vector
+(define_expand "vunsignedo_v4sf"
+  [(match_operand:V2DI 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    {
+      /* Shift left one word to put even word in correct location.  */
+      rtx rtx_tmp = gen_reg_rtx (V4SFmode);
+      rtx rtx_val = GEN_INT (4);
+      emit_insn (gen_altivec_vsldoi_v4sf (rtx_tmp, operands[1], operands[1],
+                                         rtx_val));
+      emit_insn (gen_vsx_xvcvspuxds_be (operands[0], rtx_tmp));
+    }
+  else
+    emit_insn (gen_vsx_xvcvspuxds_le (operands[0], operands[1]));
+
+  DONE;
+})
+
 ;; Generate float2 double
 ;; convert two double to float
 (define_expand "float2_v2df"

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index b2e41a581dd1c2d32e750a46e68d00727ec40806..98e3966662aec976e19448036ca7c5ac6ae28911 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22649,6 +22649,16 @@ if the VSX instruction set is available.  The @samp{vec_vsx_ld} and
 @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
 @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
 
+@smallexample
+vector signed long long vec_signedo (vector float);
+vector signed long long vec_signede (vector float);
+vector unsigned long long vec_unsignedo (vector float);
+vector unsigned long long vec_unsignede (vector float);
+@end smallexample
+
+The overloaded built-ins @code{vec_signedo} and @code{vec_signede} are
+additional extensions to the built-ins as documented in the PVIPR.
+
 @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
 @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
 

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
index 5dcdfbee7916c52cd05e576b00c287869ce59a0f..5c2481dd612890a862ddc198990437a195fbf8e5 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
@@ -81,14 +81,15 @@ void test_unsigned_int_result(int check, vector unsigned int vec_result,
 }
 
 void test_ll_int_result(vector long long int vec_result,
-                       vector long long int vec_expected)
+                       vector long long int vec_expected,
+                       char *string)
 {
        int i;
 
        for (i = 0; i < 2; i++)
                if (vec_result[i] != vec_expected[i]) {
 #ifdef DEBUG
-                       printf("Test_ll_int_result: ");
+                       printf("Test_ll_int_result %s: ", string);
                        printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n",
                               i, vec_result[i], i, vec_expected[i]);
 #else
@@ -98,14 +99,15 @@ void test_ll_int_result(vector long long int vec_result,
 }
 
 void test_ll_unsigned_int_result(vector long long unsigned int vec_result,
-                                vector long long unsigned int vec_expected)
+                                vector long long unsigned int vec_expected,
+                                char *string)
 {
        int i;
 
        for (i = 0; i < 2; i++)
                if (vec_result[i] != vec_expected[i]) {
 #ifdef DEBUG
-                       printf("Test_ll_unsigned_int_result: ");
+                       printf("Test_ll_unsigned_int_result %s: ", string);
                        printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n",
                               i, vec_result[i], i, vec_expected[i]);
 #else
@@ -292,7 +294,8 @@ int main()
        vec_dble0 = (vector double){-124.930, 81234.49};
        vec_ll_int_expected = (vector long long signed int){-124, 81234};
        vec_ll_int_result = vec_signed (vec_dble0);
-       test_ll_int_result (vec_ll_int_result, vec_ll_int_expected);
+       test_ll_int_result (vec_ll_int_result, vec_ll_int_expected,
+                           "vec_signed");
 
        /* Convert double precision vector float to vector int, even words */
        vec_dble0 = (vector double){-124.930, 81234.49};
@@ -321,12 +324,44 @@ int main()
        test_unsigned_int_result (ALL, vec_uns_int_result,
                                  vec_uns_int_expected);
 
+       /* Convert single precision vector float, even args, to vector
+          signed long long int.  */
+       vec_flt0 = (vector float){14.930, 834.49, -3.3, -5.4};
+       vec_ll_int_expected = (vector signed long long int){14, -3};
+       vec_ll_int_result = vec_signede (vec_flt0);
+       test_ll_int_result (vec_ll_int_result, vec_ll_int_expected,
+                           "vec_signede");
+
+       /* Convert single precision vector float, odd args, to vector
+          signed long long int.  */
+       vec_flt0 = (vector float){14.930, 834.49, -3.3, -5.4};
+       vec_ll_int_expected = (vector signed long long int){834, -5};
+       vec_ll_int_result = vec_signedo (vec_flt0);
+       test_ll_int_result (vec_ll_int_result, vec_ll_int_expected,
+                           "vec_signedo");
+
+       /* Convert single precision vector float, even args, to vector
+          unsigned long long int.  */
+       vec_flt0 = (vector float){14.930, 834.49, -3.3, -5.4};
+       vec_ll_uns_int_expected = (vector unsigned long long int){14, 0};
+       vec_ll_uns_int_result = vec_unsignede (vec_flt0);
+       test_ll_unsigned_int_result (vec_ll_uns_int_result,
+                                    vec_ll_uns_int_expected, "vec_unsignede");
+
+       /* Convert single precision vector float, odd args, to vector
+          unsigned long long int.  */
+       vec_flt0 = (vector float){14.930, 834.49, -3.3, -5.4};
+       vec_ll_uns_int_expected = (vector unsigned long long int){834, 0};
+       vec_ll_uns_int_result = vec_unsignedo (vec_flt0);
+       test_ll_unsigned_int_result (vec_ll_uns_int_result,
+                                    vec_ll_uns_int_expected, "vec_unsignedo");
+
        /* Convert double precision float to long long unsigned int */
        vec_dble0 = (vector double){124.930, 8134.49};
        vec_ll_uns_int_expected = (vector long long unsigned int){124, 8134};
        vec_ll_uns_int_result = vec_unsigned (vec_dble0);
        test_ll_unsigned_int_result (vec_ll_uns_int_result,
-                                    vec_ll_uns_int_expected);
+                                    vec_ll_uns_int_expected, "vec_unsigned");
 
        /* Convert double precision float to long long unsigned int. Negative
           arguments.  */
@@ -334,7 +369,7 @@ int main()
        vec_ll_uns_int_expected = (vector long long unsigned int){0, 0};
        vec_ll_uns_int_result = vec_unsigned (vec_dble0);
        test_ll_unsigned_int_result (vec_ll_uns_int_result,
-                                    vec_ll_uns_int_expected);
+                                    vec_ll_uns_int_expected, "vec_unsigned");
 
        /* Convert double precision vector float to vector unsigned int,
           even words.  Negative arguments */