]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 9 Jun 2025 22:56:22 +0000 (23:56 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 20 Aug 2025 16:41:19 +0000 (18:41 +0200)
[ Upstream commit e37a95d01d5acce211da8446fefbd8684c67f516 ]

The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

index dc6ab012cdb69f92a33da69638aef3fc6fdfa46c..6aca10920c8e3f9e68958cfbe7365d4db23e51e9 100644 (file)
@@ -585,6 +585,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
        if (mode->clock > 148500)
                return MODE_CLOCK_HIGH;
 
+       if (mode->clock < 5803)
+               return MODE_CLOCK_LOW;
+
        return MODE_OK;
 }