]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/display: convert HAS_DOUBLE_BUFFERED_M_N() to struct intel_display
authorJani Nikula <jani.nikula@intel.com>
Mon, 11 Nov 2024 10:33:53 +0000 (12:33 +0200)
committerJani Nikula <jani.nikula@intel.com>
Tue, 12 Nov 2024 07:58:52 +0000 (09:58 +0200)
Convert HAS_DOUBLE_BUFFERED_M_N() to struct intel_display. Do minimal
drive-by conversions to struct intel_display in the callers while at it.

v2: Rebase

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d313d32ae411b86eedb86c4a4949dc84588362df.1731321183.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_device.h
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/display/intel_drrs.c

index 46f6643d8d0f5b0cf5bbee850afe1bcf29d83ff9..e338bbaa36fd6e6cae6391cb00723adc1d2ae30d 100644 (file)
@@ -5322,6 +5322,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
                          const struct intel_crtc_state *pipe_config,
                          bool fastset)
 {
+       struct intel_display *display = to_intel_display(current_config);
        struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
        struct drm_printer p;
@@ -5562,7 +5563,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        PIPE_CONF_CHECK_I(lane_count);
        PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-       if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
+       if (HAS_DOUBLE_BUFFERED_M_N(display)) {
                if (!fastset || !pipe_config->update_m_n)
                        PIPE_CONF_CHECK_M_N(dp_m_n);
        } else {
index 5176d109251a1484638be3460ff94b9360c6c7eb..78a93c7193e42891598b53b82bbcdaa4f4a420f7 100644 (file)
@@ -150,7 +150,7 @@ struct intel_display_platforms {
 #define HAS_DISPLAY(i915)              (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
 #define HAS_DMC(i915)                  (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
 #define HAS_DMC_WAKELOCK(i915)         (DISPLAY_VER(i915) >= 20)
-#define HAS_DOUBLE_BUFFERED_M_N(i915)  (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+#define HAS_DOUBLE_BUFFERED_M_N(__display)     (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell)
 #define HAS_DOUBLE_WIDE(i915)          (DISPLAY_VER(i915) < 4)
 #define HAS_DP_MST(i915)               (DISPLAY_INFO(i915)->has_dp_mst)
 #define HAS_DP20(i915)                 (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
index 95c71e425fbef1c7ad5acbca4161a6424b02a9ff..565ddaffb64e19cd012fd2b6d06db89058a9d2d3 100644 (file)
@@ -1719,13 +1719,13 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 
 static bool has_seamless_m_n(struct intel_connector *connector)
 {
-       struct drm_i915_private *i915 = to_i915(connector->base.dev);
+       struct intel_display *display = to_intel_display(connector);
 
        /*
         * Seamless M/N reprogramming only implemented
         * for BDW+ double buffered M/N registers so far.
         */
-       return HAS_DOUBLE_BUFFERED_M_N(i915) &&
+       return HAS_DOUBLE_BUFFERED_M_N(display) &&
                intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
 }
 
index bb39eb96e812c751d5eefc3f50d02abaa3390df8..0fec01b79b233ccaa4795f1af644d77549961f78 100644 (file)
@@ -68,7 +68,9 @@ const char *intel_drrs_type_str(enum drrs_type drrs_type)
 bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915,
                                   enum transcoder cpu_transcoder)
 {
-       if (HAS_DOUBLE_BUFFERED_M_N(i915))
+       struct intel_display *display = &i915->display;
+
+       if (HAS_DOUBLE_BUFFERED_M_N(display))
                return true;
 
        return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);