arm64: sysreg: Add layout for ICH_MISR_EL2

The ICH_MISR_EL2-related macros are missing a number of status
bits that we are about to handle. Take this opportunity to fully
describe the layout of that register as part of the automatic
generation infrastructure.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250225172930.1850838-4-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b59b2c680e977381af5893ca93c4a5de6830f7cb..9511f3faac462d846b3d908e904e4dacac2b835b 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -562,7 +562,6 @@
 
 #define SYS_ICH_VSEIR_EL2              sys_reg(3, 4, 12, 9, 4)
 #define SYS_ICC_SRE_EL2                        sys_reg(3, 4, 12, 9, 5)
-#define SYS_ICH_MISR_EL2               sys_reg(3, 4, 12, 11, 2)
 #define SYS_ICH_EISR_EL2               sys_reg(3, 4, 12, 11, 3)
 #define SYS_ICH_ELRSR_EL2              sys_reg(3, 4, 12, 11, 5)
 #define SYS_ICH_VMCR_EL2               sys_reg(3, 4, 12, 11, 7)
@@ -983,10 +982,6 @@
 #define SYS_MPIDR_SAFE_VAL     (BIT(31))
 
 /* GIC Hypervisor interface registers */
-/* ICH_MISR_EL2 bit definitions */
-#define ICH_MISR_EOI           (1 << 0)
-#define ICH_MISR_U             (1 << 1)
-
 /* ICH_LR*_EL2 bit definitions */
 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
 

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 3e82a072eb4938424e62a897f9520a81b37999ca..2c63662c1a489826afe408ba69f3469c559d8af4 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -3071,6 +3071,18 @@ Res0     17:5
 Field  4:0     ListRegs
 EndSysreg
 
+Sysreg ICH_MISR_EL2    3       4       12      11      2
+Res0   63:8
+Field  7       VGrp1D
+Field  6       VGrp1E
+Field  5       VGrp0D
+Field  4       VGrp0E
+Field  3       NP
+Field  2       LRENP
+Field  1       U
+Field  0       EOI
+EndSysreg
+
 Sysreg CONTEXTIDR_EL2  3       4       13      0       1
 Fields CONTEXTIDR_ELx
 EndSysreg

diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
index 5d9d7e394b25492e016cf5d05ef7e98f5b8e5e3f..b6c5ece4fdee74b75b71aedf0201e0c9fea35e44 100644 (file)
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@ -558,7 +558,6 @@
 
 #define SYS_ICH_VSEIR_EL2              sys_reg(3, 4, 12, 9, 4)
 #define SYS_ICC_SRE_EL2                        sys_reg(3, 4, 12, 9, 5)
-#define SYS_ICH_MISR_EL2               sys_reg(3, 4, 12, 11, 2)
 #define SYS_ICH_EISR_EL2               sys_reg(3, 4, 12, 11, 3)
 #define SYS_ICH_ELRSR_EL2              sys_reg(3, 4, 12, 11, 5)
 #define SYS_ICH_VMCR_EL2               sys_reg(3, 4, 12, 11, 7)
@@ -979,10 +978,6 @@
 #define SYS_MPIDR_SAFE_VAL     (BIT(31))
 
 /* GIC Hypervisor interface registers */
-/* ICH_MISR_EL2 bit definitions */
-#define ICH_MISR_EOI           (1 << 0)
-#define ICH_MISR_U             (1 << 1)
-
 /* ICH_LR*_EL2 bit definitions */
 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)