[RISCV] Use constraints/predicates instead of checking const_int directly for shNadd...

This simplifies the code by adding a predicate and a constraint for 1/2/3.
The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
which they use there.

OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.

Thanks,
Andrew Pinski

gcc/ChangeLog:

	* config/riscv/constraints.md (Ds3): New constraint.
	* config/riscv/predicates.md (imm123_operand): New predicate.
	* config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
	(*shNadduw): Likewise.

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 9f3c306423d61f87bb097342c6a398852ce9163d..258bd5a84fcdd62bb5d12397030a475660ebf629 100644 (file)
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -32,10 +32,9 @@
 (define_insn "*shNadd"
   [(set (match_operand:X 0 "register_operand" "=r")
        (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
-                         (match_operand:QI 2 "immediate_operand" "I"))
+                         (match_operand:QI 2 "imm123_operand" "Ds3"))
                (match_operand:X 3 "register_operand" "r")))]
-  "TARGET_ZBA
-   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
+  "TARGET_ZBA"
   "sh%2add\t%0,%1,%3"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -44,11 +43,10 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (plus:DI
          (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-                            (match_operand:QI 2 "immediate_operand" "I"))
+                            (match_operand:QI 2 "imm123_operand" "Ds3"))
                 (match_operand 3 "immediate_operand" ""))
          (match_operand:DI 4 "register_operand" "r")))]
   "TARGET_64BIT && TARGET_ZBA
-   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
    && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
   "sh%2add.uw\t%0,%1,%4"
   [(set_attr "type" "bitmanip")

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index bafa4188ccb35333a64fea50cda7f3b0f47fd205..61b84875fd9e569c1343e11f90c1ca211a3b699f 100644 (file)
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -54,6 +54,12 @@
   (and (match_code "const_int")
        (match_test "LUI_OPERAND (ival)")))
 
+(define_constraint "Ds3"
+  "@internal
+   1, 2 or 3 immediate"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 1, 3)")))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 79e0c1d5589ddc51905ea038ce580d7356fd7360..2af7f661d6fbeb6335a35fd59f91dc8b758ffdb1 100644 (file)
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -244,6 +244,11 @@
   (and (match_code "const_int")
        (match_test "INTVAL (op) < 5")))
 
+;; A const_int for sh1add/sh2add/sh3add
+(define_predicate "imm123_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
+
 ;; A CONST_INT operand that consists of a single run of consecutive set bits.
 (define_predicate "consecutive_bits_operand"
   (match_code "const_int")