RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vssubu.vv to the
vssubu.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, FUNC)                                      \
  void                                                                \
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {                                                                   \
    for (unsigned i = 0; i < n; i++)                                  \
      out[i] = FUNC (in[i], x);                                       \
  }

  T sat_sub(T a, T b)
  {
    return (a - b) & (-(T)(a >= b));
  }

  DEF_VX_BINARY(uint32_t, sat_sub)

Before this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  14   │     slli    a3,a3,32
  15   │     srli    a3,a3,32
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  18   │     vle32.v v1,0(a1)
  19   │     slli    a4,a5,2
  20   │     sub a3,a3,a5
  21   │     add a1,a1,a4
  22   │     vssubu.vv v1,v1,v2
  23   │     vse32.v v1,0(a0)
  24   │     add a0,a0,a4
  25   │     bne a3,zero,.L3

After this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     slli    a3,a3,32
  13   │     srli    a3,a3,32
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  16   │     vle32.v v1,0(a1)
  17   │     slli    a4,a5,2
  18   │     sub a3,a3,a5
  19   │     add a1,a1,a4
  20   │     vssubu.vx v1,v1,a2
  21   │     vse32.v v1,0(a0)
  22   │     add a0,a0,a4
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vx_binary_vec_vec_dup): Add
	new case US_MINUS.
	* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
	* config/riscv/vector-iterators.md: Add new op us_minus.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a3d704e81cc4338e416620e4a9863c747dea5402..69f2a1ece534c16d4035d6c5b6529ffecb326a3b 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5583,6 +5583,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx op_2,
     case SMIN:
     case UMIN:
     case US_PLUS:
+    case US_MINUS:
       icode = code_for_pred_scalar (code, mode);
       break;
     default:

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index bbc7547d385f6c2c71fe4245e9ca6262e31ddfc9..f5d2b2e74aede28f03c54a325c5793370a01d387 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3996,6 +3996,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
                    case MOD:
                    case UMOD:
                    case US_PLUS:
+                   case US_MINUS:
                      *total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
                      break;
                    default:

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 0e1318d1447cc98ac02c7449809ec7e74819b842..782544423c41e04ca8f4ad94fdd01a9e266ba126 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,7 +4042,7 @@
 ])
 
 (define_code_iterator any_int_binop_no_shift_v_vdup [
-  plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus
+  plus minus and ior xor mult div udiv mod umod smax umax smin umin us_plus us_minus
 ])
 
 (define_code_iterator any_int_binop_no_shift_vdup_v [