--- /dev/null
+From a96c7e6b875a9c0f91b3bb15021944af0c510c74 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 12 Jan 2023 20:43:34 +0100
+Subject: cpuidle, intel_idle: Fix CPUIDLE_FLAG_IBRS
+
+From: Peter Zijlstra <peterz@infradead.org>
+
+[ Upstream commit 9b461a6faae7b220c32466261965778b10189e54 ]
+
+objtool to the rescue:
+
+ vmlinux.o: warning: objtool: intel_idle_ibrs+0x17: call to spec_ctrl_current() leaves .noinstr.text section
+ vmlinux.o: warning: objtool: intel_idle_ibrs+0x27: call to wrmsrl.constprop.0() leaves .noinstr.text section
+
+Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Tested-by: Tony Lindgren <tony@atomide.com>
+Tested-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Frederic Weisbecker <frederic@kernel.org>
+Link: https://lore.kernel.org/r/20230112195540.556912863@infradead.org
+Stable-dep-of: c157d351460b ("intel_idle: Handle older CPUs, which stop the TSC in deeper C states, correctly")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/cpu/bugs.c | 2 +-
+ drivers/idle/intel_idle.c | 4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
+index 03221a060ae77..7d73b53115514 100644
+--- a/arch/x86/kernel/cpu/bugs.c
++++ b/arch/x86/kernel/cpu/bugs.c
+@@ -92,7 +92,7 @@ void update_spec_ctrl_cond(u64 val)
+ wrmsrl(MSR_IA32_SPEC_CTRL, val);
+ }
+
+-u64 spec_ctrl_current(void)
++noinstr u64 spec_ctrl_current(void)
+ {
+ return this_cpu_read(x86_spec_ctrl_current);
+ }
+diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
+index 5d7bbccb52b5e..ae07dc018e666 100644
+--- a/drivers/idle/intel_idle.c
++++ b/drivers/idle/intel_idle.c
+@@ -188,12 +188,12 @@ static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
+ int ret;
+
+ if (smt_active)
+- wrmsrl(MSR_IA32_SPEC_CTRL, 0);
++ native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+
+ ret = __intel_idle(dev, drv, index);
+
+ if (smt_active)
+- wrmsrl(MSR_IA32_SPEC_CTRL, spec_ctrl);
++ native_wrmsrl(MSR_IA32_SPEC_CTRL, spec_ctrl);
+
+ return ret;
+ }
+--
+2.39.5
+
--- /dev/null
+From 4b3213517b57d4b8501b29954b684978df03cda4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Dec 2023 11:32:06 +0800
+Subject: drm/amdgpu: Check extended configuration space register when system
+ uses large bar
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ma Jun <Jun.Ma2@amd.com>
+
+[ Upstream commit e372baeb3d336b20fd9463784c577fd8824497cd ]
+
+Some customer platforms do not enable mmconfig for various reasons,
+such as bios bug, and therefore cannot access the GPU extend configuration
+space through mmio.
+
+When the system enters the d3cold state and resumes, the amdgpu driver
+fails to resume because the extend configuration space registers of
+GPU can't be restored. At this point, Usually we only see some failure
+dmesg log printed by amdgpu driver, it is difficult to find the root
+cause.
+
+Therefor print a warnning message if the system can't access the
+extended configuration space register when using large bar.
+
+Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: 099bffc7cadf ("drm/amdgpu: disable BAR resize on Dell G5 SE")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index c4e548d32504d..a28f7e0a27aaa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1220,6 +1220,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
++ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
++ DRM_WARN("System can't access extended configuration space,please check!!\n");
++
+ /* skip if the bios has already enabled large BAR */
+ if (adev->gmc.real_vram_size &&
+ (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
+--
+2.39.5
+
--- /dev/null
+From d1fb42eb49ac527b6249059fdf294d3216e95d21 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Feb 2025 10:55:05 -0500
+Subject: drm/amdgpu: disable BAR resize on Dell G5 SE
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+[ Upstream commit 099bffc7cadff40bfab1517c3461c53a7a38a0d7 ]
+
+There was a quirk added to add a workaround for a Sapphire
+RX 5600 XT Pulse that didn't allow BAR resizing. However,
+the quirk caused a regression with runtime pm on Dell laptops
+using those chips, rather than narrowing the scope of the
+resizing quirk, add a quirk to prevent amdgpu from resizing
+the BAR on those Dell platforms unless runtime pm is disabled.
+
+v2: update commit message, add runpm check
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1707
+Fixes: 907830b0fc9e ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse")
+Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 5235053f443cef4210606e5fb71f99b915a9723d)
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index a28f7e0a27aaa..b41a97185823a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1220,6 +1220,13 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* resizing on Dell G5 SE platforms causes problems with runtime pm */
++ if ((amdgpu_runtime_pm != 0) &&
++ adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
++ adev->pdev->device == 0x731f &&
++ adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
++ return 0;
++
+ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
+ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
+ DRM_WARN("System can't access extended configuration space,please check!!\n");
+--
+2.39.5
+
--- /dev/null
+From 01cbf34ee494caf36afd1dba712151936025ff44 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Feb 2025 15:18:39 -0500
+Subject: efi: Don't map the entire mokvar table to determine its size
+
+From: Peter Jones <pjones@redhat.com>
+
+[ Upstream commit 2b90e7ace79774a3540ce569e000388f8d22c9e0 ]
+
+Currently, when validating the mokvar table, we (re)map the entire table
+on each iteration of the loop, adding space as we discover new entries.
+If the table grows over a certain size, this fails due to limitations of
+early_memmap(), and we get a failure and traceback:
+
+ ------------[ cut here ]------------
+ WARNING: CPU: 0 PID: 0 at mm/early_ioremap.c:139 __early_ioremap+0xef/0x220
+ ...
+ Call Trace:
+ <TASK>
+ ? __early_ioremap+0xef/0x220
+ ? __warn.cold+0x93/0xfa
+ ? __early_ioremap+0xef/0x220
+ ? report_bug+0xff/0x140
+ ? early_fixup_exception+0x5d/0xb0
+ ? early_idt_handler_common+0x2f/0x3a
+ ? __early_ioremap+0xef/0x220
+ ? efi_mokvar_table_init+0xce/0x1d0
+ ? setup_arch+0x864/0xc10
+ ? start_kernel+0x6b/0xa10
+ ? x86_64_start_reservations+0x24/0x30
+ ? x86_64_start_kernel+0xed/0xf0
+ ? common_startup_64+0x13e/0x141
+ </TASK>
+ ---[ end trace 0000000000000000 ]---
+ mokvar: Failed to map EFI MOKvar config table pa=0x7c4c3000, size=265187.
+
+Mapping the entire structure isn't actually necessary, as we don't ever
+need more than one entry header mapped at once.
+
+Changes efi_mokvar_table_init() to only map each entry header, not the
+entire table, when determining the table size. Since we're not mapping
+any data past the variable name, it also changes the code to enforce
+that each variable name is NUL terminated, rather than attempting to
+verify it in place.
+
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Peter Jones <pjones@redhat.com>
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/firmware/efi/mokvar-table.c | 41 +++++++++--------------------
+ 1 file changed, 13 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/firmware/efi/mokvar-table.c b/drivers/firmware/efi/mokvar-table.c
+index 5ed0602c2f75f..d865cb1dbaad1 100644
+--- a/drivers/firmware/efi/mokvar-table.c
++++ b/drivers/firmware/efi/mokvar-table.c
+@@ -103,7 +103,6 @@ void __init efi_mokvar_table_init(void)
+ void *va = NULL;
+ unsigned long cur_offset = 0;
+ unsigned long offset_limit;
+- unsigned long map_size = 0;
+ unsigned long map_size_needed = 0;
+ unsigned long size;
+ struct efi_mokvar_table_entry *mokvar_entry;
+@@ -134,48 +133,34 @@ void __init efi_mokvar_table_init(void)
+ */
+ err = -EINVAL;
+ while (cur_offset + sizeof(*mokvar_entry) <= offset_limit) {
+- mokvar_entry = va + cur_offset;
+- map_size_needed = cur_offset + sizeof(*mokvar_entry);
+- if (map_size_needed > map_size) {
+- if (va)
+- early_memunmap(va, map_size);
+- /*
+- * Map a little more than the fixed size entry
+- * header, anticipating some data. It's safe to
+- * do so as long as we stay within current memory
+- * descriptor.
+- */
+- map_size = min(map_size_needed + 2*EFI_PAGE_SIZE,
+- offset_limit);
+- va = early_memremap(efi.mokvar_table, map_size);
+- if (!va) {
+- pr_err("Failed to map EFI MOKvar config table pa=0x%lx, size=%lu.\n",
+- efi.mokvar_table, map_size);
+- return;
+- }
+- mokvar_entry = va + cur_offset;
++ if (va)
++ early_memunmap(va, sizeof(*mokvar_entry));
++ va = early_memremap(efi.mokvar_table + cur_offset, sizeof(*mokvar_entry));
++ if (!va) {
++ pr_err("Failed to map EFI MOKvar config table pa=0x%lx, size=%zu.\n",
++ efi.mokvar_table + cur_offset, sizeof(*mokvar_entry));
++ return;
+ }
++ mokvar_entry = va;
+
+ /* Check for last sentinel entry */
+ if (mokvar_entry->name[0] == '\0') {
+ if (mokvar_entry->data_size != 0)
+ break;
+ err = 0;
++ map_size_needed = cur_offset + sizeof(*mokvar_entry);
+ break;
+ }
+
+- /* Sanity check that the name is null terminated */
+- size = strnlen(mokvar_entry->name,
+- sizeof(mokvar_entry->name));
+- if (size >= sizeof(mokvar_entry->name))
+- break;
++ /* Enforce that the name is NUL terminated */
++ mokvar_entry->name[sizeof(mokvar_entry->name) - 1] = '\0';
+
+ /* Advance to the next entry */
+- cur_offset = map_size_needed + mokvar_entry->data_size;
++ cur_offset += sizeof(*mokvar_entry) + mokvar_entry->data_size;
+ }
+
+ if (va)
+- early_memunmap(va, map_size);
++ early_memunmap(va, sizeof(*mokvar_entry));
+ if (err) {
+ pr_err("EFI MOKvar config table is not valid\n");
+ return;
+--
+2.39.5
+
--- /dev/null
+From 35e8ddd044f997b6c5f9e03cae7800c26b7b8ec0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Oct 2024 11:32:00 -0500
+Subject: ibmvnic: Inspect header requirements before using scrq direct
+
+From: Nick Child <nnac123@linux.ibm.com>
+
+[ Upstream commit de390657b5d6f7deb9d1d36aaf45f02ba51ec9dc ]
+
+Previously, the TX header requirement for standard frames was ignored.
+This requirement is a bitstring sent from the VIOS which maps to the
+type of header information needed during TX. If no header information,
+is needed then send subcrq direct can be used (which can be more
+performant).
+
+This bitstring was previously ignored for standard packets (AKA non LSO,
+non CSO) due to the belief that the bitstring was over-cautionary. It
+turns out that there are some configurations where the backing device
+does need header information for transmission of standard packets. If
+the information is not supplied then this causes continuous "Adapter
+error" transport events. Therefore, this bitstring should be respected
+and observed before considering the use of send subcrq direct.
+
+Fixes: 74839f7a8268 ("ibmvnic: Introduce send sub-crq direct")
+Signed-off-by: Nick Child <nnac123@linux.ibm.com>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://patch.msgid.link/20241001163200.1802522-2-nnac123@linux.ibm.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ibm/ibmvnic.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
+index 578b9b5460108..071dca86fc883 100644
+--- a/drivers/net/ethernet/ibm/ibmvnic.c
++++ b/drivers/net/ethernet/ibm/ibmvnic.c
+@@ -2300,9 +2300,11 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ /* if we are going to send_subcrq_direct this then we need to
+ * update the checksum before copying the data into ltb. Essentially
+ * these packets force disable CSO so that we can guarantee that
+- * FW does not need header info and we can send direct.
++ * FW does not need header info and we can send direct. Also, vnic
++ * server must be able to xmit standard packets without header data
+ */
+- if (!skb_is_gso(skb) && !ind_bufp->index && !netdev_xmit_more()) {
++ if (*hdrs == 0 && !skb_is_gso(skb) &&
++ !ind_bufp->index && !netdev_xmit_more()) {
+ use_scrq_send_direct = true;
+ if (skb->ip_summed == CHECKSUM_PARTIAL &&
+ skb_checksum_help(skb))
+--
+2.39.5
+
--- /dev/null
+From 7be077ea93bd47cac0f25a16d0622c03ed132b2b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Aug 2024 16:18:09 -0500
+Subject: ibmvnic: Perform tx CSO during send scrq direct
+
+From: Nick Child <nnac123@linux.ibm.com>
+
+[ Upstream commit e633e32b60fd6701bed73599b273a2a03621ea54 ]
+
+During initialization with the vnic server, a bitstring is communicated
+to the client regarding header info needed during CSO (See "VNIC
+Capabilities" in PAPR). Most of the time, to be safe, vnic server
+requests header info for CSO. When header info is needed, multiple TX
+descriptors are required per skb; This limits the driver to use
+send_subcrq_indirect instead of send_subcrq_direct.
+
+Previously, the vnic server request for header info was ignored. This
+allowed the use of send_sub_crq_direct. Transmissions were successful
+because the bitstring returned by vnic server is broad and over
+cautionary. It was observed that mlx backing devices could actually
+transmit and handle CSO packets without the vnic server receiving
+header info (despite the fact that the bitstring requested it).
+
+There was a trust issue: The bitstring was overcautionary. This extra
+precaution (requesting header info when the backing device may not use
+it) comes at the cost of performance (using direct vs indirect hcalls
+has a 30% delta in small packet RR transaction rate). So it has been
+requested that the vnic server team tries to ensure that the bitstring
+is more exact. In the meantime, disable CSO when it is possible to use
+the skb in the send_subcrq_direct path. In other words, calculate the
+checksum before handing the packet to FW when the packet is not
+segmented and xmit_more is false.
+
+Since the code path is only possible if the skb is non GSO and xmit_more
+is false, the cost of doing checksum in the send_subcrq_direct path is
+minimal. Any large segmented skb will have xmit_more set to true more
+frequently and it is inexpensive to do checksumming on a small skb.
+The worst-case workload would be a 9000 MTU TCP_RR test with close
+to MTU sized packets (and TSO off). This allows xmit_more to be false
+more frequently and open the code path up to use send_subcrq_direct.
+Observing trace data (graph-time = 1) and packet rate with this workload
+shows minimal performance degradation:
+
+1. NIC does checksum w headers, safely use send_subcrq_indirect:
+ - Packet rate: 631k txs
+ - Trace data:
+ ibmvnic_xmit = 44344685.87 us / 6234576 hits = AVG 7.11 us
+ skb_checksum_help = 4.07 us / 2 hits = AVG 2.04 us
+ ^ Notice hits, tracing this just for reassurance
+ ibmvnic_tx_scrq_flush = 33040649.69 us / 5638441 hits = AVG 5.86 us
+ send_subcrq_indirect = 37438922.24 us / 6030859 hits = AVG 6.21 us
+
+2. NIC does checksum w/o headers, dangerously use send_subcrq_direct:
+ - Packet rate: 831k txs
+ - Trace data:
+ ibmvnic_xmit = 48940092.29 us / 8187630 hits = AVG 5.98 us
+ skb_checksum_help = 2.03 us / 1 hits = AVG 2.03
+ ibmvnic_tx_scrq_flush = 31141879.57 us / 7948960 hits = AVG 3.92 us
+ send_subcrq_indirect = 8412506.03 us / 728781 hits = AVG 11.54
+ ^ notice hits is much lower b/c send_subcrq_direct was called
+ ^ wasn't traceable
+
+3. driver does checksum, safely use send_subcrq_direct (THIS PATCH):
+ - Packet rate: 829k txs
+ - Trace data:
+ ibmvnic_xmit = 56696077.63 us / 8066168 hits = AVG 7.03 us
+ skb_checksum_help = 8587456.16 us / 7526072 hits = AVG 1.14 us
+ ibmvnic_tx_scrq_flush = 30219545.55 us / 7782409 hits = AVG 3.88 us
+ send_subcrq_indirect = 8638326.44 us / 763693 hits = AVG 11.31 us
+
+When the bitstring ever specifies that CSO does not require headers
+(dependent on VIOS vnic server changes), then this patch should be
+removed and replaced with one that investigates the bitstring before
+using send_subcrq_direct.
+
+Signed-off-by: Nick Child <nnac123@linux.ibm.com>
+Link: https://patch.msgid.link/20240807211809.1259563-8-nnac123@linux.ibm.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: de390657b5d6 ("ibmvnic: Inspect header requirements before using scrq direct")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ibm/ibmvnic.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
+index 44991cae94045..578b9b5460108 100644
+--- a/drivers/net/ethernet/ibm/ibmvnic.c
++++ b/drivers/net/ethernet/ibm/ibmvnic.c
+@@ -2237,6 +2237,7 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ unsigned int skblen;
+ union sub_crq tx_crq;
+ unsigned int offset;
++ bool use_scrq_send_direct = false;
+ int num_entries = 1;
+ unsigned char *dst;
+ int bufidx = 0;
+@@ -2296,6 +2297,18 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ memset(dst, 0, tx_pool->buf_size);
+ data_dma_addr = ltb->addr + offset;
+
++ /* if we are going to send_subcrq_direct this then we need to
++ * update the checksum before copying the data into ltb. Essentially
++ * these packets force disable CSO so that we can guarantee that
++ * FW does not need header info and we can send direct.
++ */
++ if (!skb_is_gso(skb) && !ind_bufp->index && !netdev_xmit_more()) {
++ use_scrq_send_direct = true;
++ if (skb->ip_summed == CHECKSUM_PARTIAL &&
++ skb_checksum_help(skb))
++ use_scrq_send_direct = false;
++ }
++
+ if (skb_shinfo(skb)->nr_frags) {
+ int cur, i;
+
+@@ -2381,11 +2394,13 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ tx_crq.v1.flags1 |= IBMVNIC_TX_LSO;
+ tx_crq.v1.mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
+ hdrs += 2;
+- } else if (!ind_bufp->index && !netdev_xmit_more()) {
+- ind_bufp->indir_arr[0] = tx_crq;
++ } else if (use_scrq_send_direct) {
++ /* See above comment, CSO disabled with direct xmit */
++ tx_crq.v1.flags1 &= ~(IBMVNIC_TX_CHKSUM_OFFLOAD);
+ ind_bufp->index = 1;
+ tx_buff->num_entries = 1;
+ netdev_tx_sent_queue(txq, skb->len);
++ ind_bufp->indir_arr[0] = tx_crq;
+ lpar_rc = ibmvnic_tx_scrq_flush(adapter, tx_scrq, false);
+ if (lpar_rc != H_SUCCESS)
+ goto tx_err;
+--
+2.39.5
+
--- /dev/null
+From 062d4c9969606ee86885708e02feffd1efbf0599 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 24 Feb 2025 19:12:47 +0800
+Subject: net: enetc: VFs do not support HWTSTAMP_TX_ONESTEP_SYNC
+
+From: Wei Fang <wei.fang@nxp.com>
+
+[ Upstream commit a562d0c4a893eae3ea51d512c4d90ab858a6b7ec ]
+
+Actually ENETC VFs do not support HWTSTAMP_TX_ONESTEP_SYNC because only
+ENETC PF can access PMa_SINGLE_STEP registers. And there will be a crash
+if VFs are used to test one-step timestamp, the crash log as follows.
+
+[ 129.110909] Unable to handle kernel paging request at virtual address 00000000000080c0
+[ 129.287769] Call trace:
+[ 129.290219] enetc_port_mac_wr+0x30/0xec (P)
+[ 129.294504] enetc_start_xmit+0xda4/0xe74
+[ 129.298525] enetc_xmit+0x70/0xec
+[ 129.301848] dev_hard_start_xmit+0x98/0x118
+
+Fixes: 41514737ecaa ("enetc: add get_ts_info interface for ethtool")
+Cc: stable@vger.kernel.org
+Signed-off-by: Wei Fang <wei.fang@nxp.com>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Link: https://patch.msgid.link/20250224111251.1061098-5-wei.fang@nxp.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/freescale/enetc/enetc.c | 3 +++
+ drivers/net/ethernet/freescale/enetc/enetc_ethtool.c | 8 ++++++--
+ 2 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c
+index 230b317d93dae..fac29772b882b 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc.c
+@@ -2683,6 +2683,9 @@ static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
+ priv->active_offloads |= ENETC_F_TX_TSTAMP;
+ break;
+ case HWTSTAMP_TX_ONESTEP_SYNC:
++ if (!enetc_si_is_pf(priv->si))
++ return -EOPNOTSUPP;
++
+ priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
+ priv->active_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP;
+ break;
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+index c8369e3752b0e..7eb0a3d29f6e1 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+@@ -770,6 +770,7 @@ static int enetc_set_coalesce(struct net_device *ndev,
+ static int enetc_get_ts_info(struct net_device *ndev,
+ struct ethtool_ts_info *info)
+ {
++ struct enetc_ndev_priv *priv = netdev_priv(ndev);
+ int *phc_idx;
+
+ phc_idx = symbol_get(enetc_phc_index);
+@@ -789,8 +790,11 @@ static int enetc_get_ts_info(struct net_device *ndev,
+ SOF_TIMESTAMPING_SOFTWARE;
+
+ info->tx_types = (1 << HWTSTAMP_TX_OFF) |
+- (1 << HWTSTAMP_TX_ON) |
+- (1 << HWTSTAMP_TX_ONESTEP_SYNC);
++ (1 << HWTSTAMP_TX_ON);
++
++ if (enetc_si_is_pf(priv->si))
++ info->tx_types |= (1 << HWTSTAMP_TX_ONESTEP_SYNC);
++
+ info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+ (1 << HWTSTAMP_FILTER_ALL);
+ #else
+--
+2.39.5
+
--- /dev/null
+ibmvnic-perform-tx-cso-during-send-scrq-direct.patch
+ibmvnic-inspect-header-requirements-before-using-scr.patch
+drm-amdgpu-check-extended-configuration-space-regist.patch
+drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch
+net-enetc-vfs-do-not-support-hwtstamp_tx_onestep_syn.patch
+cpuidle-intel_idle-fix-cpuidle_flag_ibrs.patch
+x86-speculation-add-__update_spec_ctrl-helper.patch
+efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch
--- /dev/null
+From 789a852b5960da19bc2ad8fe63a81d5e9fd96e6a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 27 Jul 2023 14:45:57 -0400
+Subject: x86/speculation: Add __update_spec_ctrl() helper
+
+From: Waiman Long <longman@redhat.com>
+
+[ Upstream commit e3e3bab1844d448a239cd57ebf618839e26b4157 ]
+
+Add a new __update_spec_ctrl() helper which is a variant of
+update_spec_ctrl() that can be used in a noinstr function.
+
+Suggested-by: Peter Zijlstra <peterz@infradead.org>
+Signed-off-by: Waiman Long <longman@redhat.com>
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Link: https://lore.kernel.org/r/20230727184600.26768-2-longman@redhat.com
+Stable-dep-of: c157d351460b ("intel_idle: Handle older CPUs, which stop the TSC in deeper C states, correctly")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/include/asm/spec-ctrl.h | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h
+index cb0386fc4dc3b..c648502e45357 100644
+--- a/arch/x86/include/asm/spec-ctrl.h
++++ b/arch/x86/include/asm/spec-ctrl.h
+@@ -4,6 +4,7 @@
+
+ #include <linux/thread_info.h>
+ #include <asm/nospec-branch.h>
++#include <asm/msr.h>
+
+ /*
+ * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
+@@ -76,6 +77,16 @@ static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
+ return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
+ }
+
++/*
++ * This can be used in noinstr functions & should only be called in bare
++ * metal context.
++ */
++static __always_inline void __update_spec_ctrl(u64 val)
++{
++ __this_cpu_write(x86_spec_ctrl_current, val);
++ native_wrmsrl(MSR_IA32_SPEC_CTRL, val);
++}
++
+ #ifdef CONFIG_SMP
+ extern void speculative_store_bypass_ht_init(void);
+ #else
+--
+2.39.5
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
