clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent

The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
the rates, because this messes up entire clock hierarchy when setting
clock rates in MSM DSI driver.

The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
via dev_pm_opp_set_rate() on byte clock and then sets individual clock
rates, like pixel and byte_intf clocks, to proper frequencies.  Having
CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
clock received halved frequency.  Drop CLK_SET_RATE_PARENT to fix this
and align with SM8550 and SM8650.

Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250129154519.209791-1-krzysztof.kozlowski@linaro.org
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c
index 0358dff91da5d7f7bc662231a2ed748bbb7f1194..e9bca179998b9fb672b32f47f61092793d733457 100644 (file)
--- a/drivers/clk/qcom/dispcc-sm8750.c
+++ b/drivers/clk/qcom/dispcc-sm8750.c
@@ -827,7 +827,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
                        &disp_cc_mdss_byte0_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };
@@ -842,7 +841,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
                        &disp_cc_mdss_byte1_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };