arm.md (mulhisi3, [...]): Enable for any ARMv5e processor, not just for XScale.

* arm.md (mulhisi3, mulhisi3addsi, mulhidi3adddi): Enable for any
ARMv5e processor, not just for XScale.  Instructions are predicable.
(mulhisi3tb, mulhisi3bt, mulhisi3tt): New patterns for ARMv5e.

From-SVN: r63562

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fb08e3a0d6c2e51c9b5414e26e43fc414f3dcc2a..a059d23e50e7362df30ab77e3039e1756bf9f284 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2003-02-28  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm.md (mulhisi3, mulhisi3addsi, mulhidi3adddi): Enable for any 
+       ARMv5e processor, not just for XScale.  Instructions are predicable.
+       (mulhisi3tb, mulhisi3bt, mulhisi3tt): New patterns for ARMv5e.
+
 2003-02-28  Nick Clifton  <nickc@redhat.com>
 
        * config/arm/arm.c (note_invalid_constants): Change parameter type

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 946064ba69680f1fbe20a1418fd74f217e5652b4..e53a526b96ee8b98aa4e848e790cf3f7219ffd3d 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1329,9 +1329,50 @@
                  (match_operand:HI 1 "s_register_operand" "%r"))
                 (sign_extend:SI
                  (match_operand:HI 2 "s_register_operand" "r"))))]
-  "TARGET_ARM && arm_is_xscale"
+  "TARGET_ARM && arm_arch5e"
   "smulbb%?\\t%0, %1, %2"
-  [(set_attr "type" "mult")]
+  [(set_attr "type" "mult")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*mulhisi3tb"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+       (mult:SI (ashiftrt:SI
+                 (match_operand:SI 1 "s_register_operand" "r")
+                 (const_int 16))
+                (sign_extend:SI
+                 (match_operand:HI 2 "s_register_operand" "r"))))]
+  "TARGET_ARM && arm_arch5e"
+  "smultb%?\\t%0, %1, %2"
+  [(set_attr "type" "mult")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*mulhisi3bt"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+       (mult:SI (sign_extend:SI
+                 (match_operand:HI 1 "s_register_operand" "r"))
+                (ashiftrt:SI
+                 (match_operand:SI 2 "s_register_operand" "r")
+                 (const_int 16))))]
+  "TARGET_ARM && arm_arch5e"
+  "smulbt%?\\t%0, %1, %2"
+  [(set_attr "type" "mult")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*mulhisi3tt"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+       (mult:SI (ashiftrt:SI
+                 (match_operand:SI 1 "s_register_operand" "r")
+                 (const_int 16))
+                (ashiftrt:SI
+                 (match_operand:SI 2 "s_register_operand" "r")
+                 (const_int 16))))]
+  "TARGET_ARM && arm_arch5e"
+  "smultt%?\\t%0, %1, %2"
+  [(set_attr "type" "mult")
+   (set_attr "predicable" "yes")]
 )
 
 (define_insn "*mulhisi3addsi"
@@ -1341,9 +1382,10 @@
                           (match_operand:HI 2 "s_register_operand" "%r"))
                          (sign_extend:SI
                           (match_operand:HI 3 "s_register_operand" "r")))))]
-  "TARGET_ARM && arm_is_xscale"
+  "TARGET_ARM && arm_arch5e"
   "smlabb%?\\t%0, %2, %3, %1"
-  [(set_attr "type" "mult")]
+  [(set_attr "type" "mult")
+   (set_attr "predicable" "yes")]
 )
 
 (define_insn "*mulhidi3adddi"
@@ -1354,9 +1396,10 @@
                    (match_operand:HI 2 "s_register_operand" "%r"))
                   (sign_extend:DI
                    (match_operand:HI 3 "s_register_operand" "r")))))]
-  "TARGET_ARM && arm_is_xscale"
+  "TARGET_ARM && arm_arch5e"
   "smlalbb%?\\t%Q0, %R0, %2, %3"
-[(set_attr "type" "mult")])
+  [(set_attr "type" "mult")
+   (set_attr "predicable" "yes")])
 
 (define_insn "*arm_mulsf3"
   [(set (match_operand:SF 0 "s_register_operand" "=f")