--- /dev/null
+From 720bb6436ff30fccad05cf5bdf961ea5b1f5686d Mon Sep 17 00:00:00 2001
+From: Douglas Bagnall <douglas@paradise.net.nz>
+Date: Fri, 6 Jul 2012 23:27:57 -0300
+Subject: media: Avoid sysfs oops when an rc_dev's raw device is absent
+
+From: Douglas Bagnall <douglas@paradise.net.nz>
+
+commit 720bb6436ff30fccad05cf5bdf961ea5b1f5686d upstream.
+
+For some reason, when the lirc daemon learns that a usb remote control
+has been unplugged, it wants to read the sysfs attributes of the
+disappearing device. This is useful for uncovering transient
+inconsistencies, but less so for keeping the system running when such
+inconsistencies exist.
+
+Under some circumstances (like every time I unplug my dvb stick from
+my laptop), lirc catches an rc_dev whose raw event handler has been
+removed (presumably by ir_raw_event_unregister), and proceeds to
+interrogate the raw protocols supported by the NULL pointer.
+
+This patch avoids the NULL dereference, and ignores the issue of how
+this state of affairs came about in the first place.
+
+Version 2 incorporates changes recommended by Mauro Carvalho Chehab
+(-ENODEV instead of -EINVAL, and a signed-off-by).
+
+Signed-off-by: Douglas Bagnall <douglas@paradise.net.nz>
+Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
+Cc: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/media/rc/rc-main.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/media/rc/rc-main.c
++++ b/drivers/media/rc/rc-main.c
+@@ -775,10 +775,11 @@ static ssize_t show_protocols(struct dev
+ if (dev->driver_type == RC_DRIVER_SCANCODE) {
+ enabled = dev->rc_map.rc_type;
+ allowed = dev->allowed_protos;
+- } else {
++ } else if (dev->raw) {
+ enabled = dev->raw->enabled_protocols;
+ allowed = ir_raw_get_allowed_protocols();
+- }
++ } else
++ return -ENODEV;
+
+ IR_dprintk(1, "allowed - 0x%llx, enabled - 0x%llx\n",
+ (long long)allowed,
--- /dev/null
+From 9bc03743fff0770dc5a5324ba92e67cc377f16ca Mon Sep 17 00:00:00 2001
+From: Alan Cox <alan@linux.intel.com>
+Date: Mon, 2 Jul 2012 18:51:38 +0100
+Subject: pch_uart: Fix missing break for 16 byte fifo
+
+From: Alan Cox <alan@linux.intel.com>
+
+commit 9bc03743fff0770dc5a5324ba92e67cc377f16ca upstream.
+
+Otherwise we fall back to the wrong value.
+
+Reported-by: <dcb314@hotmail.com>
+Resolves-bug: https://bugzilla.kernel.org/show_bug.cgi?id=44091
+Signed-off-by: Alan Cox <alan@linux.intel.com>
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/pch_uart.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -1263,6 +1263,7 @@ static int pch_uart_startup(struct uart_
+ break;
+ case 16:
+ fifo_size = PCH_UART_HAL_FIFO16;
++ break;
+ case 1:
+ default:
+ fifo_size = PCH_UART_HAL_FIFO_DIS;
--- /dev/null
+From 38bd2a1ac736901d1cf4971c78ef952ba92ef78b Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Date: Fri, 6 Jul 2012 17:19:43 +0900
+Subject: pch_uart: Fix parity setting issue
+
+From: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+
+commit 38bd2a1ac736901d1cf4971c78ef952ba92ef78b upstream.
+
+Parity Setting value is reverse.
+E.G. In case of setting ODD parity, EVEN value is set.
+This patch inverts "if" condition.
+
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Acked-by: Alan Cox <alan@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/pch_uart.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -1365,7 +1365,7 @@ static void pch_uart_set_termios(struct
+ stb = PCH_UART_HAL_STB1;
+
+ if (termios->c_cflag & PARENB) {
+- if (!(termios->c_cflag & PARODD))
++ if (termios->c_cflag & PARODD)
+ parity = PCH_UART_HAL_PARITY_ODD;
+ else
+ parity = PCH_UART_HAL_PARITY_EVEN;
--- /dev/null
+From 9539dfb7ac1c84522fe1f79bb7dac2990f3de44a Mon Sep 17 00:00:00 2001
+From: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Date: Fri, 6 Jul 2012 17:19:42 +0900
+Subject: pch_uart: Fix rx error interrupt setting issue
+
+From: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+
+commit 9539dfb7ac1c84522fe1f79bb7dac2990f3de44a upstream.
+
+Rx Error interrupt(E.G. parity error) is not enabled.
+So, when parity error occurs, error interrupt is not occurred.
+As a result, the received data is not dropped.
+
+This patch adds enable/disable rx error interrupt code.
+
+Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
+Acked-by: Alan Cox <alan@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/pch_uart.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -754,7 +754,8 @@ static void pch_dma_rx_complete(void *ar
+ tty_flip_buffer_push(tty);
+ tty_kref_put(tty);
+ async_tx_ack(priv->desc_rx);
+- pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
++ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
++ PCH_UART_HAL_RX_ERR_INT);
+ }
+
+ static void pch_dma_tx_complete(void *arg)
+@@ -809,7 +810,8 @@ static int handle_rx_to(struct eg20t_por
+ int rx_size;
+ int ret;
+ if (!priv->start_rx) {
+- pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
++ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
++ PCH_UART_HAL_RX_ERR_INT);
+ return 0;
+ }
+ buf = &priv->rxbuf;
+@@ -1078,11 +1080,13 @@ static irqreturn_t pch_uart_interrupt(in
+ case PCH_UART_IID_RDR: /* Received Data Ready */
+ if (priv->use_dma) {
+ pch_uart_hal_disable_interrupt(priv,
+- PCH_UART_HAL_RX_INT);
++ PCH_UART_HAL_RX_INT |
++ PCH_UART_HAL_RX_ERR_INT);
+ ret = dma_handle_rx(priv);
+ if (!ret)
+ pch_uart_hal_enable_interrupt(priv,
+- PCH_UART_HAL_RX_INT);
++ PCH_UART_HAL_RX_INT |
++ PCH_UART_HAL_RX_ERR_INT);
+ } else {
+ ret = handle_rx(priv);
+ }
+@@ -1208,7 +1212,8 @@ static void pch_uart_stop_rx(struct uart
+ struct eg20t_port *priv;
+ priv = container_of(port, struct eg20t_port, port);
+ priv->start_rx = 0;
+- pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
++ pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
++ PCH_UART_HAL_RX_ERR_INT);
+ }
+
+ /* Enable the modem status interrupts. */
+@@ -1301,7 +1306,8 @@ static int pch_uart_startup(struct uart_
+ pch_request_dma(port);
+
+ priv->start_rx = 1;
+- pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
++ pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
++ PCH_UART_HAL_RX_ERR_INT);
+ uart_update_timeout(port, CS8, default_baud);
+
+ return 0;
--- /dev/null
+From 6269f2584a359766f53005c676daff8aee60cbed Mon Sep 17 00:00:00 2001
+From: Timur Tabi <timur@freescale.com>
+Date: Fri, 13 Jul 2012 14:28:42 -0500
+Subject: powerpc/85xx: p1022ds: disable the NAND flash node if video is enabled
+
+From: Timur Tabi <timur@freescale.com>
+
+commit 6269f2584a359766f53005c676daff8aee60cbed upstream.
+
+The Freescale P1022 has a unique pin muxing "feature" where the DIU video
+controller's video signals are muxed with 24 of the local bus address signals.
+When the DIU is enabled, the bulk of the local bus is disabled, preventing
+access to memory-mapped devices like NAND flash and the pixis FPGA.
+
+Therefore, if the DIU is going to be enabled, then memory-mapped devices on
+the localbus, like NAND flash, need to be disabled.
+
+This patch is similar to "powerpc/85xx: p1022ds: disable the NOR flash node
+if video is enabled", except that it disables the NAND flash node instead.
+This PIXIS node needs to remain enabled because it is used by platform code
+to switch into indirect mode.
+
+Signed-off-by: Timur Tabi <timur@freescale.com>
+Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+
+---
+ arch/powerpc/platforms/85xx/p1022_ds.c | 38 +++++++++++++++++++++++++--------
+ 1 file changed, 29 insertions(+), 9 deletions(-)
+
+--- a/arch/powerpc/platforms/85xx/p1022_ds.c
++++ b/arch/powerpc/platforms/85xx/p1022_ds.c
+@@ -435,6 +435,8 @@ static void __init disable_one_node(stru
+ prom_update_property(np, new, old);
+ else
+ prom_add_property(np, new);
++
++ pr_info("p1022ds: disabling %s node\n", np->full_name);
+ }
+
+ /* TRUE if there is a "video=fslfb" command-line parameter. */
+@@ -499,28 +501,46 @@ static void __init p1022_ds_setup_arch(v
+ diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
+
+ /*
+- * Disable the NOR flash node if there is video=fslfb... command-line
+- * parameter. When the DIU is active, NOR flash is unavailable, so we
+- * have to disable the node before the MTD driver loads.
++ * Disable the NOR and NAND flash nodes if there is video=fslfb...
++ * command-line parameter. When the DIU is active, the localbus is
++ * unavailable, so we have to disable these nodes before the MTD
++ * driver loads.
+ */
+ if (fslfb) {
+ struct device_node *np =
+ of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
+
+ if (np) {
+- np = of_find_compatible_node(np, NULL, "cfi-flash");
+- if (np) {
++ struct device_node *np2;
++
++ of_node_get(np);
++ np2 = of_find_compatible_node(np, NULL, "cfi-flash");
++ if (np2) {
+ static struct property nor_status = {
+ .name = "status",
+ .value = "disabled",
+ .length = sizeof("disabled"),
+ };
+
+- pr_info("p1022ds: disabling %s node",
+- np->full_name);
+- disable_one_node(np, &nor_status);
+- of_node_put(np);
++ disable_one_node(np2, &nor_status);
++ of_node_put(np2);
++ }
++
++ of_node_get(np);
++ np2 = of_find_compatible_node(np, NULL,
++ "fsl,elbc-fcm-nand");
++ if (np2) {
++ static struct property nand_status = {
++ .name = "status",
++ .value = "disabled",
++ .length = sizeof("disabled"),
++ };
++
++ disable_one_node(np2, &nand_status);
++ of_node_put(np2);
+ }
++
++ of_node_put(np);
+ }
+
+ }
--- /dev/null
+From 896c01cb4bb3cfc2c0ea9873fa7a9f8bd0a7c8d8 Mon Sep 17 00:00:00 2001
+From: Timur Tabi <timur@freescale.com>
+Date: Mon, 23 Jul 2012 15:43:32 -0500
+Subject: powerpc/85xx: p1022ds: fix DIU/LBC switching with NAND enabled
+
+From: Timur Tabi <timur@freescale.com>
+
+commit 896c01cb4bb3cfc2c0ea9873fa7a9f8bd0a7c8d8 upstream.
+
+In order for indirect mode on the PIXIS to work properly, both chip selects
+need to be set to GPCM mode, otherwise writes to the chip select base
+addresses will not actually post to the local bus -- they'll go to the
+NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM
+mode before switching to indirect mode.
+
+Signed-off-by: Timur Tabi <timur@freescale.com>
+Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/powerpc/platforms/85xx/p1022_ds.c | 64 +++++++++++++++++++++++++++++++--
+ 1 file changed, 62 insertions(+), 2 deletions(-)
+
+--- a/arch/powerpc/platforms/85xx/p1022_ds.c
++++ b/arch/powerpc/platforms/85xx/p1022_ds.c
+@@ -208,6 +208,7 @@ static void p1022ds_set_monitor_port(enu
+ u8 __iomem *lbc_lcs0_ba = NULL;
+ u8 __iomem *lbc_lcs1_ba = NULL;
+ phys_addr_t cs0_addr, cs1_addr;
++ u32 br0, or0, br1, or1;
+ const __be32 *iprop;
+ unsigned int num_laws;
+ u8 b;
+@@ -256,11 +257,70 @@ static void p1022ds_set_monitor_port(enu
+ }
+ num_laws = be32_to_cpup(iprop);
+
+- cs0_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[0].br));
+- cs1_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[1].br));
++ /*
++ * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
++ * otherwise writes to these addresses won't actually appear on the
++ * local bus, and so the PIXIS won't see them.
++ *
++ * In FCM mode, writes go to the NAND controller, which does not pass
++ * them to the localbus directly. So we force BR0 and BR1 into GPCM
++ * mode, since we don't care about what's behind the localbus any
++ * more.
++ */
++ br0 = in_be32(&lbc->bank[0].br);
++ br1 = in_be32(&lbc->bank[1].br);
++ or0 = in_be32(&lbc->bank[0].or);
++ or1 = in_be32(&lbc->bank[1].or);
++
++ /* Make sure CS0 and CS1 are programmed */
++ if (!(br0 & BR_V) || !(br1 & BR_V)) {
++ pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
++ goto exit;
++ }
++
++ /*
++ * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
++ * force the values to simple 32KB GPCM windows with the most
++ * conservative timing.
++ */
++ if ((br0 & BR_MSEL) != BR_MS_GPCM) {
++ br0 = (br0 & BR_BA) | BR_V;
++ or0 = 0xFFFF8000 | 0xFF7;
++ out_be32(&lbc->bank[0].br, br0);
++ out_be32(&lbc->bank[0].or, or0);
++ }
++ if ((br1 & BR_MSEL) != BR_MS_GPCM) {
++ br1 = (br1 & BR_BA) | BR_V;
++ or1 = 0xFFFF8000 | 0xFF7;
++ out_be32(&lbc->bank[1].br, br1);
++ out_be32(&lbc->bank[1].or, or1);
++ }
++
++ cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
++ if (!cs0_addr) {
++ pr_err("p1022ds: could not determine physical address for CS0"
++ " (BR0=%08x)\n", br0);
++ goto exit;
++ }
++ cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
++ if (!cs0_addr) {
++ pr_err("p1022ds: could not determine physical address for CS1"
++ " (BR1=%08x)\n", br1);
++ goto exit;
++ }
+
+ lbc_lcs0_ba = ioremap(cs0_addr, 1);
++ if (!lbc_lcs0_ba) {
++ pr_err("p1022ds: could not ioremap CS0 address %llx\n",
++ (unsigned long long)cs0_addr);
++ goto exit;
++ }
+ lbc_lcs1_ba = ioremap(cs1_addr, 1);
++ if (!lbc_lcs1_ba) {
++ pr_err("p1022ds: could not ioremap CS1 address %llx\n",
++ (unsigned long long)cs1_addr);
++ goto exit;
++ }
+
+ /* Make sure we're in indirect mode first. */
+ if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
time-improve-sanity-checking-of-timekeeping-inputs.patch
time-avoid-making-adjustments-if-we-haven-t-accumulated-anything.patch
time-move-ktime_t-overflow-checking-into-timespec_valid_strict.patch
+media-avoid-sysfs-oops-when-an-rc_dev-s-raw-device-is-absent.patch
+pch_uart-fix-missing-break-for-16-byte-fifo.patch
+pch_uart-fix-rx-error-interrupt-setting-issue.patch
+pch_uart-fix-parity-setting-issue.patch
+powerpc-85xx-p1022ds-disable-the-nand-flash-node-if-video-is-enabled.patch
+powerpc-85xx-p1022ds-fix-diu-lbc-switching-with-nand-enabled.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
